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litedram
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https://github.com/enjoy-digital/litedram.git
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dad2c972f7
litedram
/
bench
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Florent Kermarrec
379db85fc7
bench: Update with LiteX/LiteX-Boards changes.
2022-12-08 10:29:43 +01:00
..
arty.py
bench/targets: Use full imports.
2022-05-02 13:07:29 +02:00
common.py
bench: Update with LiteX/LiteX-Boards changes.
2022-12-08 10:29:43 +01:00
ddr3_mr_gen.py
ddr3_mr_gen: Also display RZQ/x on configured electrical settings.
2022-02-24 16:33:46 +01:00
ddr4_mr_gen.py
bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).
2020-11-06 14:44:36 +01:00
genesys2.py
bench/targets: Use full imports.
2022-05-02 13:07:29 +02:00
kc705.py
bench/targets: Use full imports.
2022-05-02 13:07:29 +02:00
kcu105.py
bench/targets: Use full imports.
2022-05-02 13:07:29 +02:00
xcu1525.py
bench: Update with LiteX/LiteX-Boards changes.
2022-12-08 10:29:43 +01:00