174 lines
8.5 KiB
Python
174 lines
8.5 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.gen.sim import run_simulation
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from litex.soc.interconnect import avalon
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from litedram.frontend.avalon import LiteDRAMAvalonMM2Native
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from litedram.common import LiteDRAMNativePort
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from test.common import DRAMMemory, MemoryTestDataMixin
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class DUT(Module):
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def __init__(self, port, avalon, base_address=0x0, mem_expected=[]):
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self.port = port
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self.avalon = avalon
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self.submodules += LiteDRAMAvalonMM2Native(
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avalon = self.avalon,
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port = self.port,
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base_address = base_address)
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self.mem = DRAMMemory(port.data_width, len(mem_expected))
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class TestAvalon(MemoryTestDataMixin, unittest.TestCase):
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def avalon_readback_test(self, pattern, mem_expected, avalon, port, base_address=0):
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def main_generator(dut):
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for adr, data in pattern:
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yield from dut.avalon.bus_write(adr, data)
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data_r = (yield from dut.avalon.bus_read(adr))
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self.assertEqual(data_r, data)
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dut = DUT(port, avalon, base_address, mem_expected)
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generators = [
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main_generator(dut),
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dut.mem.write_handler(dut.port),
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dut.mem.read_handler(dut.port),
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]
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run_simulation(dut, generators, vcd_name='sim.vcd')
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self.assertEqual(dut.mem.mem, mem_expected)
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def test_avalon_8bit(self):
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# Verify AvalonMM with 8-bit data width.
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data = self.pattern_test_data["8bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=8)
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port = LiteDRAMNativePort("both", address_width=30, data_width=8)
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self.avalon_readback_test(data["pattern"], data["expected"], avl, port)
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def test_avalon_32bit(self):
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# Verify AvalonMM with 32-bit data width.
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data = self.pattern_test_data["32bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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self.avalon_readback_test(data["pattern"], data["expected"], avl, port)
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def test_avalon_64bit(self):
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# Verify AvalonMM with 64-bit data width.
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data = self.pattern_test_data["64bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=64)
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port = LiteDRAMNativePort("both", address_width=30, data_width=64)
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self.avalon_readback_test(data["pattern"], data["expected"], avl, port)
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def test_avalon_64bit_to_32bit(self):
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# Verify AvalonMM with 64-bit data width down-converted to 32-bit data width.
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data = self.pattern_test_data["64bit_to_32bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=64)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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self.avalon_readback_test(data["pattern"], data["expected"], avl, port)
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def test_avalon_64bit_to_32bit_base_address(self):
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# Verify AvalonMM with 64-bit data width down-converted to 32-bit data width and non-zero base address.
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data = self.pattern_test_data["64bit_to_32bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=64)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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origin = 0x10000000
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pattern = [(adr + origin//(64//8), data) for adr, data in data["pattern"]]
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self.avalon_readback_test(pattern, data["expected"], avl, port, base_address=origin)
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def test_avalon_32bit_to_8bit(self):
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# Verify AvalonMM with 32-bit data width down-converted to 8-bit data width.
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data = self.pattern_test_data["32bit_to_8bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=8)
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self.avalon_readback_test(data["pattern"], data["expected"], avl, port)
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def test_avalon_32bit_to_8bit_base_address(self):
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# Verify AvalonMM with 32-bit data width down-converted to 8-bit data width and non-zero base address.
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data = self.pattern_test_data["32bit_to_8bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=8)
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origin = 0x10000000
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pattern = [(adr + origin//(32//8), data) for adr, data in data["pattern"]]
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self.avalon_readback_test(pattern, data["expected"], avl, port, base_address=origin)
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def test_avalon_8bit_to_32bit(self):
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# Verify AvalonMM with 8-bit data width up-converted to 32-bit data width.
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data = self.pattern_test_data["8bit_to_32bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=8)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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self.avalon_readback_test(data["pattern"], data["expected"], avl, port)
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def test_avalon_32bit_to_64bit(self):
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# Verify AvalonMM with 32-bit data width up-converted to 64-bit data width.
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data = self.pattern_test_data["32bit_to_64bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=64)
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self.avalon_readback_test(data["pattern"], data["expected"], avl, port)
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def test_avalon_32bit_to_128bit(self):
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# Verify AvalonMM with 32-bit data width up-converted to 128-bit data width.
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data = self.pattern_test_data["32bit_to_128bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=128)
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self.avalon_readback_test(data["pattern"], data["expected"], avl, port)
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def test_avalon_32bit_to_256bit(self):
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# Verify AvalonMM with 32-bit data width up-converted to 128-bit data width.
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data = self.pattern_test_data["32bit_to_256bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=256)
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self.avalon_readback_test(data["pattern"], data["expected"], avl, port)
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def test_avalon_32bit_base_address(self):
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# Verify AvalonMM with 32-bit data width and non-zero base address.
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data = self.pattern_test_data["32bit"]
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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origin = 0x10000000
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# add offset (in data words)
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pattern = [(adr + origin//(32//8), data) for adr, data in data["pattern"]]
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self.avalon_readback_test(pattern, data["expected"], avl, port, base_address=origin)
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def test_avalon_burst(self):
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data = [0x01234567, 0x89abcdef, 0xdeadbeef, 0xc0ffee00, 0x76543210]
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def main_generator(dut):
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yield from dut.avalon.bus_write(0x0, data)
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yield
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self.assertEqual((yield from dut.avalon.bus_read(0x0000, burstcount=5)), 0x01234567)
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self.assertEqual((yield dut.avalon.readdatavalid), 1)
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self.assertEqual((yield from dut.avalon.continue_read_burst()), 0x89abcdef)
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self.assertEqual((yield dut.avalon.readdatavalid), 1)
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self.assertEqual((yield from dut.avalon.continue_read_burst()), 0xdeadbeef)
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self.assertEqual((yield dut.avalon.readdatavalid), 1)
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self.assertEqual((yield from dut.avalon.continue_read_burst()), 0xc0ffee00)
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self.assertEqual((yield dut.avalon.readdatavalid), 1)
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self.assertEqual((yield from dut.avalon.continue_read_burst()), 0x76543210)
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yield
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yield
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yield
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yield
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self.assertEqual((yield from dut.avalon.bus_read(0x0000)), 0x01234567)
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self.assertEqual((yield from dut.avalon.bus_read(0x0001)), 0x89abcdef)
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self.assertEqual((yield from dut.avalon.bus_read(0x0002)), 0xdeadbeef)
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self.assertEqual((yield from dut.avalon.bus_read(0x0003)), 0xc0ffee00)
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self.assertEqual((yield from dut.avalon.bus_read(0x0004)), 0x76543210)
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yield
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yield
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avl = avalon.AvalonMMInterface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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dut = DUT(port, avl, base_address=0x0, mem_expected=data)
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generators = [
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main_generator(dut),
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dut.mem.write_handler(dut.port),
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dut.mem.read_handler(dut.port),
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]
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run_simulation(dut, generators, vcd_name='sim.vcd')
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self.assertEqual(dut.mem.mem, data)
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