178 lines
6.4 KiB
Python
178 lines
6.4 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.gen.sim import *
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from litedram.common import *
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from litedram.frontend.dma import *
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from test.common import *
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class DMAWriterDriver:
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def __init__(self, dma):
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self.dma = dma
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def write(self, pattern):
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yield self.dma.sink.valid.eq(1)
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for adr, data in pattern:
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yield self.dma.sink.address.eq(adr)
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yield self.dma.sink.data.eq(data)
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while not (yield self.dma.sink.ready):
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yield
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yield
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yield self.dma.sink.valid.eq(0)
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@staticmethod
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def wait_complete(port, n):
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for _ in range(n):
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while not (yield port.wdata.ready):
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yield
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yield
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class DMAReaderDriver:
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def __init__(self, dma):
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self.dma = dma
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self.data = []
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def read(self, address_list):
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n_last = len(self.data)
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yield self.dma.sink.valid.eq(1)
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for adr in address_list:
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yield self.dma.sink.address.eq(adr)
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while not (yield self.dma.sink.ready):
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yield
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while (yield self.dma.sink.ready):
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yield
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yield self.dma.sink.valid.eq(0)
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while len(self.data) < n_last + len(address_list):
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yield
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@passive
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def read_handler(self):
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yield self.dma.source.ready.eq(1)
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while True:
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if (yield self.dma.source.valid):
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self.data.append((yield self.dma.source.data))
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yield
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class TestDMA(MemoryTestDataMixin, unittest.TestCase):
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# LiteDRAMDMAWriter ----------------------------------------------------------------------------
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def dma_writer_test(self, pattern, mem_expected, data_width, **kwargs):
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class DUT(Module):
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def __init__(self):
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self.port = LiteDRAMNativeWritePort(address_width=32, data_width=data_width)
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self.submodules.dma = LiteDRAMDMAWriter(self.port, **kwargs)
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dut = DUT()
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driver = DMAWriterDriver(dut.dma)
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mem = DRAMMemory(data_width, len(mem_expected))
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generators = [
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driver.write(pattern),
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driver.wait_complete(dut.port, len(pattern)),
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mem.write_handler(dut.port),
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]
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run_simulation(dut, generators)
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self.assertEqual(mem.mem, mem_expected)
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def test_dma_writer_single(self):
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# Verify DMAWriter with a single 32-bit data.
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pattern = [(0x04, 0xdeadc0de)]
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mem_expected = [0] * 32
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mem_expected[0x04] = 0xdeadc0de
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self.dma_writer_test(pattern, mem_expected, data_width=32)
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def test_dma_writer_multiple(self):
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# Verify DMAWriter with multiple 32-bit datas.
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data = self.pattern_test_data["32bit"]
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self.dma_writer_test(data["pattern"], data["expected"], data_width=32)
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def test_dma_writer_sequential(self):
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# Verify DMAWriter with sequential 32-bit datas.
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data = self.pattern_test_data["32bit_sequential"]
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self.dma_writer_test(data["pattern"], data["expected"], data_width=32)
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def test_dma_writer_long_sequential(self):
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# Verify DMAWriter with long sequential 32-bit datas.
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data = self.pattern_test_data["32bit_long_sequential"]
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self.dma_writer_test(data["pattern"], data["expected"], data_width=32)
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def test_dma_writer_no_fifo(self):
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# Verify DMAWriter without FIFO.
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data = self.pattern_test_data["32bit_long_sequential"]
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self.dma_writer_test(data["pattern"], data["expected"], data_width=32, fifo_depth=1)
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def test_dma_writer_fifo_buffered(self):
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# Verify DMAWriter with a buffered FIFO.
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data = self.pattern_test_data["32bit_long_sequential"]
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self.dma_writer_test(data["pattern"], data["expected"], data_width=32, fifo_buffered=True)
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def test_dma_writer_duplicates(self):
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# Verify DMAWriter with a duplicate addresses.
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data = self.pattern_test_data["32bit_duplicates"]
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self.dma_writer_test(data["pattern"], data["expected"], data_width=32)
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# LiteDRAMDMAReader ----------------------------------------------------------------------------
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def dma_reader_test(self, pattern, mem_expected, data_width, **kwargs):
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class DUT(Module):
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def __init__(self):
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self.port = LiteDRAMNativeReadPort(address_width=32, data_width=data_width)
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self.submodules.dma = LiteDRAMDMAReader(self.port, **kwargs)
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dut = DUT()
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driver = DMAReaderDriver(dut.dma)
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mem = DRAMMemory(data_width, len(mem_expected), init=mem_expected)
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generators = [
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driver.read([adr for adr, data in pattern]),
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driver.read_handler(),
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mem.read_handler(dut.port),
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]
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run_simulation(dut, generators)
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self.assertEqual(driver.data, [data for adr, data in pattern])
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def test_dma_reader_single(self):
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# Verify DMAReader with a single 32-bit data.
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pattern = [(0x04, 0xdeadc0de)]
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mem_expected = [0] * 32
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mem_expected[0x04] = 0xdeadc0de
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self.dma_reader_test(pattern, mem_expected, data_width=32)
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def test_dma_reader_multiple(self):
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# Verify DMAReader with multiple 32-bit datas.
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data = self.pattern_test_data["32bit"]
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self.dma_reader_test(data["pattern"], data["expected"], data_width=32)
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def test_dma_reader_sequential(self):
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# Verify DMAReader with sequential 32-bit datas.
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data = self.pattern_test_data["32bit_sequential"]
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self.dma_reader_test(data["pattern"], data["expected"], data_width=32)
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def test_dma_reader_long_sequential(self):
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# Verify DMAReader with long sequential 32-bit datas.
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data = self.pattern_test_data["32bit_long_sequential"]
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self.dma_reader_test(data["pattern"], data["expected"], data_width=32)
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def test_dma_reader_no_fifo(self):
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# Verify DMAReader without FIFO.
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data = self.pattern_test_data["32bit_long_sequential"]
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self.dma_reader_test(data["pattern"], data["expected"], data_width=32, fifo_depth=1)
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def test_dma_reader_fifo_buffered(self):
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# Verify DMAReader with a buffered FIFO.
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data = self.pattern_test_data["32bit_long_sequential"]
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self.dma_reader_test(data["pattern"], data["expected"], data_width=32, fifo_buffered=True)
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