88 lines
2.6 KiB
Python
88 lines
2.6 KiB
Python
# This file is part of LiteDRAM.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litedram.phy.sim_utils import PulseTiming
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class TestSimUtils(unittest.TestCase):
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def pulse_timing_test(self, dut, *, trigger, ready, ready_p, generators=None):
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generators = generators or []
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assert len(trigger) == len(ready) == len(ready_p)
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ready_hist = ""
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ready_p_hist = ""
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def generator():
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nonlocal ready_hist, ready_p_hist
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for i in range(len(trigger)):
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yield dut.trigger.eq(int(trigger[i]))
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yield
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ready_hist += str((yield dut.ready))
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ready_p_hist += str((yield dut.ready_p))
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run_simulation(dut, [generator(), *generators])
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self.assertEqual(ready_hist, ready)
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self.assertEqual(ready_p_hist, ready_p)
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def test_pulse_timing_basic(self):
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self.pulse_timing_test(PulseTiming(4),
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trigger = "01000000",
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ready = "00000111",
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ready_p = "00000100",
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)
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def test_pulse_timing_1(self):
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self.pulse_timing_test(PulseTiming(1),
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trigger = "01000000",
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ready = "00111111",
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ready_p = "00100000",
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)
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def test_pulse_timing_0(self):
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self.pulse_timing_test(PulseTiming(0),
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trigger = "01000000",
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ready = "01111111",
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ready_p = "01000000",
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)
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def pulse_timing_signal_test(self, t, **kwargs):
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class Dut(PulseTiming):
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def __init__(self):
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self.t = Signal(3)
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super().__init__(self.t)
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dut = Dut()
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def generator():
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yield
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yield dut.t.eq(t)
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yield
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self.pulse_timing_test(dut, generators=[generator()], **kwargs)
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def test_pulse_timing_signal(self):
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self.pulse_timing_signal_test(
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t = 4,
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trigger = "00100000000000000",
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ready = "00000011111111111",
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ready_p = "00000010000000000",
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)
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def test_pulse_timing_signal_1(self):
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self.pulse_timing_signal_test(
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t = 1,
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trigger = "00100000000000000",
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ready = "00011111111111111",
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ready_p = "00010000000000000",
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)
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def test_pulse_timing_signal_0(self):
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self.pulse_timing_signal_test(
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t = 0,
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trigger = "00100000000000000",
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ready = "00111111111111111",
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ready_p = "00100000000000000",
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)
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