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liteeth/examples/axi-lite-mii.yml

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add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file)
2022-10-31 19:43:53 -04:00
#
# This file is part of LiteEth.
#
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
# PHY ----------------------------------------------------------------------
examples: Improve identation/presentation.
2024-03-18 08:43:11 -04:00
phy : LiteEthPHYMII
vendor : xilinx
toolchain : vivado
add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file)
2022-10-31 19:43:53 -04:00
# Core ---------------------------------------------------------------------
examples: Improve identation/presentation.
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clk_freq : 100e6
core : axi-lite
endianness : big
add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file)
2022-10-31 19:43:53 -04:00
examples: Improve identation/presentation.
2024-03-18 08:43:11 -04:00
# SoC ---------------------------------------------------------------------
add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file)
2022-10-31 19:43:53 -04:00
soc:
mem_map:
ethmac: 0x50000000