572 lines
22 KiB
Python
572 lines
22 KiB
Python
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2021 Leon Schuermann <leon@is.currently.online>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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import random
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import csv
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from pathlib import Path
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from migen import *
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from litex.soc.interconnect.stream import *
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from liteeth.phy.xgmii import LiteEthPHYXGMII, LiteEthPHYXGMIIRX
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from .test_stream import StreamPacket, stream_inserter, stream_collector, \
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compare_packets
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def mask_last_be(dw, data, last_be):
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"""Mark some data by a last_be data qualifier. The rest of the data
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passed in will be zeroed.
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"""
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masked_data = 0
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for byte in range(dw // 8):
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if 2**byte > last_be:
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break
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masked_data |= data & (0xFF << (byte * 8))
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return masked_data
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class XGMIICollector:
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def __init__(self, min_interframegap=12, tolerate_dic=True,
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debug_print=False):
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# Minimum IFG legal to be accepted on the XGMII interface (excluding
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# DIC, if tolerated). On the receiving send, when accounting for
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# potential IFG shrinkage and allowing the minimum receive IFG as
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# mandated by IEEE 802.3 (e.g. `min_interframegap` = 5 bytes IFG for
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# 10Gbit/s Ethernet), tolerate_dic should thus be disabled.
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self.min_interframegap = min_interframegap
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# Whether the collector should spit out debug information about received
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# signal states. Will always print error conditions.
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self.debug_print = debug_print
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# Whether the deficit idle count mechanism should be tolerated. This
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# will allow the receiver to temporarily accept IFGs < 12 bytes, as long
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# as an average inter-frame gap of >= 12 is maintained. This must be
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# implemented as a 2-bit counter, as per IEEE 802.3-2018, section four,
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# 46.3.1.4 Start control character alignment.
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self.tolerate_dic = tolerate_dic
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# Proper deficit idle count, implemented as a two bit counter using the
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# algorithm described by Eric Lynskey of the UNH InterOperability
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# Lab[1]:
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#
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# | current | | | | |
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# | count | 0 | 1 | 2 | 3 |
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# |---------+-----+-------+-----+-------+-----+-------+-----+-------|
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# | | | new | | new | | new | | new |
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# | pkt % 4 | IFG | count | IFG | count | IFG | count | IFG | count |
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# |---------+-----+-------+-----+-------+-----+-------+-----+-------|
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# | 0 | 12 | 0 | 12 | 1 | 12 | 2 | 12 | 3 |
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# | 1 | 11 | 1 | 11 | 2 | 11 | 3 | 15 | 0 |
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# | 2 | 10 | 2 | 10 | 3 | 14 | 0 | 14 | 1 |
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# | 3 | 9 | 3 | 13 | 0 | 13 | 1 | 13 | 2 |
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#
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# [1]: https://www.iol.unh.edu/sites/default/files/knowledgebase/10gec/10GbE_DIC.pdf
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self.dic = 0
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# How many additional IDLE characters we've seen. We are faithful that
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# the device is complying and initialize this to the mandated IFG byte
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# count + 3 bytes extra IDLE characters inserted through DIC, in case we
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# listen in to a captured stream and a new packet starts immediately.
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self.interframegap = 15
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# Received packets, array of arrays of bytes.
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self.packets = []
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# Packet currently being received. Array of bytes.
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self.current_packet = None
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# History of observed inter-frame gaps for debugging purposes.
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self.interframegaps = []
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# Whether the collector is currently collecting data or done. This can
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# be very useful information for designing composite test systems and
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# running until all data has been gathered.
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self.collecting = False
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def inject_32b_bus_word(self, ctl_word, data_word):
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for i in range(4):
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ctl = (ctl_word >> i) & 1
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data = (data_word >> (i * 8)) & 0xFF
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if ctl == 0 and self.current_packet is not None:
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# Data byte _and_ currently reading a packet, all fine!
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self.current_packet += [data]
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elif ctl == 1 and data == 0xFB:
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# XGMII start of frame control character
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if self.current_packet is not None:
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raise ValueError("Got start of frame control character "
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+ "while reading packet")
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if i != 0:
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raise ValueError("Got start of frame control character on "
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+ "lane {}".format(i))
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# Check and validate the observed IFG
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if self.tolerate_dic:
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if self.interframegap < self.min_interframegap:
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# Produced some deficit, check if it's legal
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self.dic += self.min_interframegap - self.interframegap
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if self.dic > 3:
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raise ValueError("DIC bounds exceeded. Observed {} "
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+ "bytes IFG, but DIC would have "
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+ "allowed {}.".format(
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self.interfamegap,
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3 - self.dic))
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elif self.interframegap > self.min_interframegap:
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# Inserted some extra IDLE, subtract from the deficit
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self.dic = min(0, self.dic - (
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self.interframegap - self.min_interframegap
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))
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elif self.interframegap < self.min_interframegap:
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# DIC is disabled
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raise ValueError("IFG violated. Oberserved {} bytes, which "
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+ "is less than the minimum of {}".format(
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self.interframegap,
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self.min_interframegap
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))
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# Store the observed IFG for debugging purposes and reset it
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self.interframegaps += [self.interframegap]
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self.interframegap = 0
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# Start a new packet. The XGMII start of frame character
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# replaces the first preamble octet, so store that as the first
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# byte.
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self.current_packet = [0x55]
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elif ctl == 1 and data == 0xFD:
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# XGMII end of frame control character
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if self.current_packet is None:
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if len(self.packets) == 0 and self.debug_print:
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print("INFO: got end of frame control character while "
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+ "not reading a packet. This can be valid for "
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+ "the first partial packet in the capture, but "
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+ "not afterwards.")
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elif len(self.packets) != 0:
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raise ValueError("Got end of frame control character "
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+ "while not reading a packet.")
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else:
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if self.debug_print:
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print("Received XGMII packet {}.".format(
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len(self.packets)
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))
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# Transmission ended, store the packet and reset the current
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# packet.
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self.packets += [self.current_packet]
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self.current_packet = None
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# The XGMII end of frame control character does count
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# towards the IFG
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self.interframegap = 1
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# All following bytes MUST be XGMII IDLE control
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# characters. We will want to verify that and
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# count the number of bytes until i % 4 == 0
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# towards the DIC counter.
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end_of_frame = True
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elif ctl == 1 and data == 0x07:
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# XGMII idle control character
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if self.current_packet is not None:
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raise ValueError("Got idle control character in the middle "
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+ "of a packet")
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self.interframegap += 1
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elif ctl == 1:
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# Unrecognized XGMII control character
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raise ValueError("Invalid XGMII control character {:02x}"
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.format(data))
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def inject_bus_word(self, dw, ctl_word, data_word):
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if dw == 32:
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self.inject_32b_bus_word(ctl_word, data_word)
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elif dw == 64:
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self.inject_32b_bus_word(
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ctl_word & 0xF,
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data_word & 0xFFFFFFFF
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)
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self.inject_32b_bus_word(
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(ctl_word >> 4) & 0xF,
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(data_word >> 32) & 0xFFFFFFFF,
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)
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else:
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raise ValueError("Unknown data width: {} bits".format(dw))
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def collect(self, xgmii_interface, tap_signals="tx", stop_cond=None):
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self.collecting = True
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# Which signals to attach to in the passed XGMII interface
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assert tap_signals in ["tx", "rx"]
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if stop_cond is None:
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stop_cond = lambda: False
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while not stop_cond():
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if tap_signals == "tx":
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ctl_word = yield xgmii_interface.tx_ctl
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data_word = yield xgmii_interface.tx_data
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dw = len(xgmii_interface.tx_data)
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elif tap_signals == "rx":
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ctl_word = yield xgmii_interface.rx_ctl
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data_word = yield xgmii_interface.rx_data
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dw = len(xgmii_interface.rx_data)
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self.inject_bus_word(dw, ctl_word, data_word)
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yield
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self.collecting = False
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class XGMII64bCSVReader:
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def __init__(self, filename, extract_signals_pattern="rx",
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complete_trailing_transaction=True):
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# Whether we should attempt to complete a trailing XGMII transaction by
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# inserting an XGMII end control character.
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self.complete_trailing_transaction = complete_trailing_transaction
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# Store filename for reference
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self.filename = filename
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# Open the CSV file and create a CSV reader over it
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self.filehandle = open(filename, 'r')
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self.reader = csv.reader(
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# Support comments in the CSV file
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filter(lambda line: not line.startswith("#"), self.filehandle),
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delimiter=','
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)
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# Extract the headers and correlate them with the required signal
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# pattern to find out the matching columns
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self.column_headers = next(self.reader, None)
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assert self.column_headers is not None, \
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"Failed to load column header row from CSV"
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self.rx_ctl_col = None
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self.rx_data_col = None
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for i, header in enumerate(self.column_headers):
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if "{}_ctl".format(extract_signals_pattern) in header:
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self.rx_ctl_col = i
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elif "{}_data".format(extract_signals_pattern) in header:
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self.rx_data_col = i
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assert self.rx_ctl_col is not None, \
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"Failed to find RX CTL signal column in CSV"
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assert self.rx_data_col is not None, \
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"Failed to find RX DATA signal column in CSV"
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self.datatype_headers = next(self.reader, None)
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assert self.datatype_headers is not None, \
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"Failed to load data type header row from CSV"
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assert self.datatype_headers[self.rx_ctl_col] == "HEX", \
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"XGMII CTL signal is not hex-encoded"
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assert self.datatype_headers[self.rx_data_col] == "HEX", \
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"XGMII DATA signal is not hex-encoded"
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# Whether the inserter is currently in the middle of a packet
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self.currently_in_packet = False
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# Hack around Python not having a peekable iterator by always taking the
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# next element at the end of a function.
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self.next_row = next(self.reader, None)
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# Upper XGMII bus word, for when 32 bit words are accessed
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self.upper_ctl = None
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self.upper_data = None
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def __del__(self):
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self.filehandle.close()
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def get_64b_bus_word(self):
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if self.next_row is None:
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return None
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ctl_word = int(self.next_row[self.rx_ctl_col], 16)
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data_word = int(self.next_row[self.rx_data_col], 16)
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new_packet = False
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# Detect whether this is just starting a new packet
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for i in range(8):
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ctl = (ctl_word >> i) & 1
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data = (data_word >> (i * 8)) & 0xFF
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if ctl == 1 and data == 0xFB:
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new_packet = True
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self.currently_in_packet = True
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if ctl == 1 and data == 0xFD:
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self.currently_in_packet = False
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# Store for below
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prev_row = self.next_row
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self.next_row = next(self.reader, None)
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# Let's make sure we have now half / dangling packet at the end. If this
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# was the last column and we're currently receiving one, make sure we
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# end it properly. This might go terribly wrong if this is condition
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# aries at the start of a packet though, in this case just throw an
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# error.
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if self.next_row is None and self.currently_in_packet \
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and self.complete_trailing_transaction:
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if new_packet:
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raise ValueError("CSV ends just at the start of a new packet, "
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+ "we can't handle that!")
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self.next_row = prev_row
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self.next_row[self.rx_ctl_col] = "ff"
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self.next_row[self.rx_data_col] = "07070707070707fd"
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return (ctl_word, data_word)
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def get_bus_word(self, dw=64):
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if dw == 64:
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assert self.upper_data is None and self.upper_ctl is None, \
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"Cannot query 32bit and 64bit bus words interchangeably"
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return self.get_64b_bus_word()
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elif dw == 64:
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if self.upper_data is not None:
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assert self.upper_ctl is not None
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return (self.upper_ctl, self.upper_data)
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else:
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xgmii_64b = self.get_64b_bus_word()
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self.upper_ctl = (xgmii_64b[0] >> 4) & 0xF
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self.upper_data = (xgmii_64b[1] >> 32) & 0xFFFFFFFF
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return (
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xgmii_64b[0] & 0xF,
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xgmii_64b[1] & 0xFFFFFFFF,
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)
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else:
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raise ValueError("Unknown dw {}!".format(dw))
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def done(self):
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return self.next_row is None
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def inject(self, xgmii_interface, stop_cond=None):
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proper_stop_cond = True
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if stop_cond is None:
|
||
|
|
proper_stop_cond = False
|
||
|
|
stop_cond = lambda: False
|
||
|
|
|
||
|
|
while not self.done():
|
||
|
|
if stop_cond():
|
||
|
|
return
|
||
|
|
|
||
|
|
(ctl, data) = self.get_bus_word(len(xgmii_interface.rx_data))
|
||
|
|
yield xgmii_interface.rx_ctl.eq(ctl)
|
||
|
|
yield xgmii_interface.rx_data.eq(data)
|
||
|
|
yield
|
||
|
|
|
||
|
|
while self.done() and proper_stop_cond and not stop_cond():
|
||
|
|
yield xgmii_interface.rx_ctl.eq(0xFF)
|
||
|
|
yield xgmii_interface.rx_data.eq(0x0707070707070707)
|
||
|
|
yield
|
||
|
|
|
||
|
|
|
||
|
|
class TestXGMIIPHY(unittest.TestCase):
|
||
|
|
def test_xgmii_rx(self):
|
||
|
|
# Read XGMII data from the CSV file
|
||
|
|
csv_file = Path(__file__).parent / "assets" / "xgmii_bus_capture.csv"
|
||
|
|
xgmii_injector = XGMII64bCSVReader(
|
||
|
|
csv_file.resolve(),
|
||
|
|
complete_trailing_transaction=True
|
||
|
|
)
|
||
|
|
|
||
|
|
# Collect the XGMII transactions from the reader with a minimum
|
||
|
|
# inter-frame gap of 5 (accounted for potential IFG shrinkage).
|
||
|
|
xgmii_collector = XGMIICollector(
|
||
|
|
min_interframegap=5,
|
||
|
|
tolerate_dic=False,
|
||
|
|
debug_print=True,
|
||
|
|
)
|
||
|
|
|
||
|
|
# XGMII interface
|
||
|
|
xgmii_interface = Record([
|
||
|
|
("rx_ctl", 8),
|
||
|
|
("rx_data", 64),
|
||
|
|
("tx_ctl", 8),
|
||
|
|
("tx_data", 64),
|
||
|
|
])
|
||
|
|
|
||
|
|
# We simply test the receiver component (XGMII -> stream) here.
|
||
|
|
dut = LiteEthPHYXGMIIRX(
|
||
|
|
xgmii_interface,
|
||
|
|
64,
|
||
|
|
)
|
||
|
|
|
||
|
|
recvd_packets = []
|
||
|
|
run_simulation(
|
||
|
|
dut,
|
||
|
|
[
|
||
|
|
xgmii_injector.inject(
|
||
|
|
xgmii_interface,
|
||
|
|
),
|
||
|
|
xgmii_collector.collect(
|
||
|
|
xgmii_interface,
|
||
|
|
tap_signals="rx",
|
||
|
|
stop_cond=lambda: xgmii_injector.done() \
|
||
|
|
and xgmii_collector.current_packet is None,
|
||
|
|
),
|
||
|
|
stream_collector(
|
||
|
|
dut.source,
|
||
|
|
dest=recvd_packets,
|
||
|
|
stop_cond=xgmii_injector.done,
|
||
|
|
seed=42,
|
||
|
|
debug_print=True,
|
||
|
|
# The XGMII PHY RX part deliberately does not support a
|
||
|
|
# deasserted ready signal. The sink is assumed to be always
|
||
|
|
# ready.
|
||
|
|
ready_rand=0,
|
||
|
|
),
|
||
|
|
],
|
||
|
|
)
|
||
|
|
|
||
|
|
self.assertTrue(
|
||
|
|
len(recvd_packets) == len(xgmii_collector.packets),
|
||
|
|
"Different number of received and sent packets: {} vs. {}!"
|
||
|
|
.format(len(recvd_packets), len(xgmii_collector.packets))
|
||
|
|
)
|
||
|
|
for p, (recvd, sent) in enumerate(
|
||
|
|
zip(recvd_packets, xgmii_collector.packets)):
|
||
|
|
self.assertTrue(
|
||
|
|
len(recvd.data) == len(sent),
|
||
|
|
("Packet sent and received with different length: {} vs. {} "
|
||
|
|
+ "at packet {}!"
|
||
|
|
).format(len(recvd.data), len(sent), p)
|
||
|
|
)
|
||
|
|
for i, (a, b) in enumerate(zip(recvd.data, sent)):
|
||
|
|
self.assertTrue(
|
||
|
|
a == b,
|
||
|
|
("Byte sent and received differ: {} vs. {} at {} byte of "
|
||
|
|
+ "packet {}"
|
||
|
|
).format(a, b, i, p)
|
||
|
|
)
|
||
|
|
|
||
|
|
def test_xgmii_stream_loopback(self):
|
||
|
|
# Read XGMII data from the CSV file
|
||
|
|
csv_file = Path(__file__).parent / "assets" / "xgmii_bus_capture.csv"
|
||
|
|
xgmii_injector = XGMII64bCSVReader(
|
||
|
|
csv_file.resolve(),
|
||
|
|
complete_trailing_transaction=True
|
||
|
|
)
|
||
|
|
|
||
|
|
# Collect the XGMII transactions from the CSV reader with a minimum
|
||
|
|
# inter-frame gap of 5 (accounted for potential IFG shrinkage).
|
||
|
|
xgmii_rx_collector = XGMIICollector(
|
||
|
|
min_interframegap=5,
|
||
|
|
tolerate_dic=False,
|
||
|
|
|
||
|
|
debug_print=True
|
||
|
|
)
|
||
|
|
|
||
|
|
# Collect the XGMII transactions from the TX PHY with a minimum
|
||
|
|
# inter-frame gap of 5. As a dumb loopback (akin to the behavior of a
|
||
|
|
# repeater) this is the smallest IPG value which may be put on the wire
|
||
|
|
# again.
|
||
|
|
xgmii_tx_collector = XGMIICollector(
|
||
|
|
min_interframegap=12,
|
||
|
|
tolerate_dic=True,
|
||
|
|
debug_print=True
|
||
|
|
)
|
||
|
|
|
||
|
|
class DUT(Module):
|
||
|
|
def __init__(self):
|
||
|
|
# XGMII signals
|
||
|
|
self.xgmii_interface = Record([
|
||
|
|
("rx_ctl", 8),
|
||
|
|
("rx_data", 64),
|
||
|
|
("tx_ctl", 8),
|
||
|
|
("tx_data", 64),
|
||
|
|
])
|
||
|
|
|
||
|
|
# PHY with TX and RX side
|
||
|
|
self.submodules.ethphy = ClockDomainsRenamer({
|
||
|
|
"eth_tx": "sys",
|
||
|
|
"eth_rx": "sys",
|
||
|
|
})(LiteEthPHYXGMII(
|
||
|
|
Record([("rx", 1), ("tx", 1)]),
|
||
|
|
self.xgmii_interface,
|
||
|
|
model=True,
|
||
|
|
))
|
||
|
|
|
||
|
|
# Insert a synchronous FIFO to allow some variability of the
|
||
|
|
# inter-frame gap. If it overflows we know that we're not
|
||
|
|
# processing data at line rate, thus we must make sure that we
|
||
|
|
# detect such a case.
|
||
|
|
self.submodules.loopback_fifo = SyncFIFO(
|
||
|
|
self.ethphy.source.payload.layout,
|
||
|
|
4,
|
||
|
|
True,
|
||
|
|
)
|
||
|
|
|
||
|
|
self.comb += [
|
||
|
|
self.ethphy.source.connect(self.loopback_fifo.sink),
|
||
|
|
self.loopback_fifo.source.connect(self.ethphy.sink),
|
||
|
|
]
|
||
|
|
|
||
|
|
dut = DUT()
|
||
|
|
run_simulation(
|
||
|
|
dut,
|
||
|
|
[
|
||
|
|
xgmii_rx_collector.collect(
|
||
|
|
dut.xgmii_interface,
|
||
|
|
tap_signals="rx",
|
||
|
|
stop_cond=lambda: xgmii_injector.done() \
|
||
|
|
and xgmii_rx_collector.current_packet is None,
|
||
|
|
),
|
||
|
|
xgmii_tx_collector.collect(
|
||
|
|
dut.xgmii_interface,
|
||
|
|
tap_signals="tx",
|
||
|
|
stop_cond=lambda: xgmii_injector.done() \
|
||
|
|
and xgmii_tx_collector.current_packet is None \
|
||
|
|
and len(xgmii_tx_collector.packets) \
|
||
|
|
>= len(xgmii_rx_collector.packets),
|
||
|
|
),
|
||
|
|
xgmii_injector.inject(
|
||
|
|
dut.xgmii_interface,
|
||
|
|
stop_cond=lambda: not xgmii_rx_collector.collecting \
|
||
|
|
and not xgmii_tx_collector.collecting,
|
||
|
|
),
|
||
|
|
],
|
||
|
|
)
|
||
|
|
|
||
|
|
self.assertTrue(
|
||
|
|
len(xgmii_rx_collector.packets) == len(xgmii_tx_collector.packets),
|
||
|
|
"Different number of sent and received packets: {} vs. {}!"
|
||
|
|
.format(len(xgmii_rx_collector.packets),
|
||
|
|
len(xgmii_tx_collector.packets))
|
||
|
|
)
|
||
|
|
for p, (recvd, sent) in enumerate(
|
||
|
|
zip(xgmii_tx_collector.packets, xgmii_rx_collector.packets)):
|
||
|
|
self.assertTrue(
|
||
|
|
len(recvd) == len(sent),
|
||
|
|
("Packet sent and received with different length: {} vs. {} at "
|
||
|
|
+ "packet {}!"
|
||
|
|
).format(len(recvd), len(sent), p)
|
||
|
|
)
|
||
|
|
for i, (a, b) in enumerate(zip(recvd, sent)):
|
||
|
|
self.assertTrue(
|
||
|
|
a == b,
|
||
|
|
("Byte sent and received differ: {} vs. {} at {} byte of "
|
||
|
|
+ "packet {}"
|
||
|
|
).format(a, b, i, p)
|
||
|
|
)
|