88 lines
2.8 KiB
Python
88 lines
2.8 KiB
Python
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#!/usr/bin/env python3
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.sim import SimPlatform
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from litex.build.sim.config import SimConfig
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.phy.model import LiteEthPHYModel
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("sys_clk", 0, Pins(1)),
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("sys_rst", 0, Pins(1)),
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("eth_clocks", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1)),
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),
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("eth", 0,
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Subsignal("source_valid", Pins(1)),
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Subsignal("source_ready", Pins(1)),
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Subsignal("source_data", Pins(8)),
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Subsignal("sink_valid", Pins(1)),
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Subsignal("sink_ready", Pins(1)),
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Subsignal("sink_data", Pins(8)),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(SimPlatform):
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def __init__(self):
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SimPlatform.__init__(self, "SIM", _io)
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, **kwargs):
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platform = Platform()
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sys_clk_freq = int(1e6)
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# SoCMini ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
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ident = "LiteEth bench Simulation",
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ident_version = True
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)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("sys_clk"))
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
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self.add_csr("ethphy")
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self.add_etherbone(phy=self.ethphy, buffer_depth=255)
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# SRAM -------------------------------------------------------------------------------------
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self.add_ram("sram", 0x20000000, 0x1000)
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# Main ---------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteEth Bench Simulation")
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args = parser.parse_args()
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sim_config = SimConfig()
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sim_config.add_clocker("sys_clk", freq_hz=1e6)
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sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.50"})
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soc = BenchSoC()
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builder = Builder(soc, csr_csv="csr.csv")
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builder.build(sim_config=sim_config)
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if __name__ == "__main__":
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main()
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