2015-11-12 17:09:37 -05:00
|
|
|
from migen import *
|
|
|
|
|
|
|
|
from litex.soc.interconnect import wishbone
|
2015-09-07 07:28:02 -04:00
|
|
|
|
2015-09-08 03:50:45 -04:00
|
|
|
from liteeth.common import *
|
|
|
|
from liteeth.core.mac import LiteEthMAC
|
|
|
|
from liteeth.core.arp import LiteEthARP
|
2015-09-07 07:28:02 -04:00
|
|
|
|
2015-09-12 14:53:14 -04:00
|
|
|
from test.common import *
|
|
|
|
from test.model import phy, mac, arp
|
2015-09-07 07:28:02 -04:00
|
|
|
|
|
|
|
ip_address = 0x12345678
|
|
|
|
mac_address = 0x12345678abcd
|
|
|
|
|
|
|
|
|
|
|
|
class TB(Module):
|
|
|
|
def __init__(self):
|
|
|
|
self.submodules.phy_model = phy.PHY(8, debug=False)
|
|
|
|
self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
|
|
|
|
self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
|
|
|
|
|
|
|
|
self.submodules.mac = LiteEthMAC(self.phy_model, dw=8, with_preamble_crc=True)
|
|
|
|
self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address, 100000)
|
|
|
|
|
|
|
|
|
2015-11-12 17:09:37 -05:00
|
|
|
def main_generator(dut):
|
|
|
|
while (yield dut.arp.table.request.ack) != 1:
|
|
|
|
yield dut.arp.table.request.stb.eq(1)
|
|
|
|
yield dut.arp.table.request.ip_address.eq(0x12345678)
|
|
|
|
yield
|
|
|
|
yield dut.arp.table.request.stb.eq(0)
|
|
|
|
while (yield dut.arp.table.response.stb) != 1:
|
|
|
|
yield dut.arp.table.response.ack.eq(1)
|
|
|
|
yield
|
|
|
|
print("Received MAC : 0x{:12x}".format((yield dut.arp.table.response.mac_address)))
|
2015-09-07 07:28:02 -04:00
|
|
|
|
2015-11-12 17:09:37 -05:00
|
|
|
# XXX: find a way to exit properly
|
|
|
|
import sys
|
|
|
|
sys.exit()
|
2015-09-07 07:28:02 -04:00
|
|
|
|
|
|
|
if __name__ == "__main__":
|
2015-11-12 17:09:37 -05:00
|
|
|
tb = TB()
|
|
|
|
generators = {
|
|
|
|
"sys" : [main_generator(tb)],
|
|
|
|
"eth_tx": [tb.phy_model.phy_sink.generator(),
|
|
|
|
tb.phy_model.generator()],
|
|
|
|
"eth_rx": tb.phy_model.phy_source.generator()
|
|
|
|
}
|
|
|
|
clocks = {"sys": 10,
|
|
|
|
"eth_rx": 10,
|
|
|
|
"eth_tx": 10}
|
|
|
|
run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
|