2022-04-25 08:26:43 -04:00
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#!/usr/bin/env python3
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import gsd_butterstick
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from litex_boards.targets.gsd_butterstick import _CRG
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from litex.soc.cores.clock import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6)):
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platform = gsd_butterstick.Platform()
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# SoCMini ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
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ident = "LiteEth bench on Butterstick",
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ident_version = True
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)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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tx_delay = 0e-9,
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with_hw_init_reset = False)
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self.add_etherbone(phy=self.ethphy, buffer_depth=255)
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# SRAM -------------------------------------------------------------------------------------
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self.add_ram("sram", 0x20000000, 0x1000)
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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self.comb += platform.request("user_led_color").eq(0b010) # Blue.
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq
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)
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2022-04-25 09:38:55 -04:00
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# JTAGBone ---------------------------------------------------------------------------------
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self.add_jtagbone()
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# Analyzer ---------------------------------------------------------------------------------
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from litescope import LiteScopeAnalyzer
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ethcore = self.ethcore_etherbone
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etherbone = self.etherbone
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self.submodules.analyzer = LiteScopeAnalyzer([
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# MAC.
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ethcore.mac.core.sink.valid,
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ethcore.mac.core.sink.ready,
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ethcore.mac.core.source.valid,
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ethcore.mac.core.source.ready,
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# ARP.
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ethcore.arp.rx.sink.valid,
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ethcore.arp.rx.sink.ready,
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ethcore.arp.tx.source.valid,
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ethcore.arp.tx.source.ready,
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# IP.
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ethcore.ip.rx.sink.valid,
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ethcore.ip.rx.sink.ready,
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ethcore.ip.tx.source.valid,
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ethcore.ip.tx.source.ready,
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# UDP.
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ethcore.udp.rx.sink.valid,
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ethcore.udp.rx.sink.ready,
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ethcore.udp.tx.source.valid,
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ethcore.udp.tx.source.ready,
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# Etherbone.
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etherbone.packet.rx.sink.valid,
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etherbone.packet.rx.sink.ready,
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etherbone.packet.rx.fsm,
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etherbone.packet.tx.source.valid,
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etherbone.packet.tx.source.ready,
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etherbone.packet.tx.fsm,
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etherbone.record.receiver.fsm,
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etherbone.record.sender.fsm
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],
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depth=512)
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2022-04-25 08:26:43 -04:00
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# Main ---------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteEth Bench on Butterstick")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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args = parser.parse_args()
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soc = BenchSoC()
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builder = Builder(soc, csr_csv="csr.csv")
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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