2020-08-23 10:06:55 -04:00
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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2019-06-24 05:43:10 -04:00
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2017-01-19 08:33:24 -05:00
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import unittest
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2018-02-23 07:40:09 -05:00
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from migen import *
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2015-11-13 09:11:57 -05:00
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.stream_sim import *
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2015-09-08 03:50:45 -04:00
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from liteeth.common import *
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from liteeth.core import LiteEthUDPIPCore
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from liteeth.frontend.etherbone import LiteEthEtherbone
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from test.model import phy, mac, arp, ip, udp, etherbone
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from litex.gen.sim import *
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ip_address = 0x12345678
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mac_address = 0x12345678abcd
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class DUT(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
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self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False)
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self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=False)
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self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False)
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self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
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self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 0x1234)
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self.submodules.sram = wishbone.SRAM(1024)
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self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.wishbone.bus, self.sram.bus)
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def main_generator(dut):
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test_probe = True
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test_writes = True
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test_reads = True
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# test probe
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if test_probe:
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packet = etherbone.EtherbonePacket()
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packet.pf = 1
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dut.etherbone_model.send(packet)
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yield from dut.etherbone_model.receive()
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print("probe: " + str(bool(dut.etherbone_model.rx_packet.pr)))
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for i in range(2):
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# test writes
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if test_writes:
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writes_datas = [j for j in range(4)]
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writes = etherbone.EtherboneWrites(base_addr=0x1000, datas=writes_datas)
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record = etherbone.EtherboneRecord()
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record.writes = writes
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record.reads = None
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record.bca = 0
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record.rca = 0
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record.rff = 0
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record.cyc = 0
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record.wca = 0
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record.wff = 0
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record.byte_enable = 0xf
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record.wcount = len(writes_datas)
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record.rcount = 0
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packet = etherbone.EtherbonePacket()
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packet.records = [record]
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dut.etherbone_model.send(packet)
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for i in range(256):
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yield
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# test reads
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if test_reads:
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reads_addrs = [0x1000 + 4*j for j in range(4)]
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reads = etherbone.EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
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record = etherbone.EtherboneRecord()
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record.writes = None
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record.reads = reads
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record.bca = 0
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record.rca = 0
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record.rff = 0
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record.cyc = 0
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record.wca = 0
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record.wff = 0
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record.byte_enable = 0xf
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record.wcount = 0
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record.rcount = len(reads_addrs)
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packet = etherbone.EtherbonePacket()
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packet.records = [record]
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dut.etherbone_model.send(packet)
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yield from dut.etherbone_model.receive()
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loopback_writes_datas = []
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loopback_writes_datas = dut.etherbone_model.rx_packet.records.pop().writes.get_datas()
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# check resultss
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s, l, e = check(writes_datas, loopback_writes_datas)
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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2017-01-19 08:33:24 -05:00
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class TestEtherbone(unittest.TestCase):
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def test_etherbone(self):
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dut = DUT()
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generators = {
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"sys" : [main_generator(dut)],
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"eth_tx": [dut.phy_model.phy_sink.generator(),
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dut.phy_model.generator()],
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"eth_rx": dut.phy_model.phy_source.generator()
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}
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clocks = {"sys": 10,
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"eth_rx": 10,
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"eth_tx": 10}
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2020-12-17 13:06:11 -05:00
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#run_simulation(dut, generators, clocks, vcd_name="sim.vcd") # FIXME: hanging
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