2015-11-13 09:11:57 -05:00
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from litex.gen import *
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2015-11-13 08:48:42 -05:00
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from litex.gen.sim.generic import run_simulation
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2015-09-07 07:28:02 -04:00
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2015-11-13 09:11:57 -05:00
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from litex.soc.interconnect import wishbone
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2015-09-08 03:50:45 -04:00
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from liteeth.common import *
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from liteeth.core.mac.core import LiteEthMACCore
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2015-09-07 07:28:02 -04:00
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2015-09-12 14:53:14 -04:00
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from test.common import *
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from test.model import phy, mac
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2015-09-07 07:28:02 -04:00
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class TB(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
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self.submodules.core = LiteEthMACCore(phy=self.phy_model, dw=8, with_preamble_crc=True)
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self.submodules.streamer = PacketStreamer(eth_phy_description(8), last_be=1)
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self.submodules.streamer_randomizer = AckRandomizer(eth_phy_description(8), level=50)
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self.submodules.logger_randomizer = AckRandomizer(eth_phy_description(8), level=50)
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self.submodules.logger = PacketLogger(eth_phy_description(8))
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2015-11-13 08:47:57 -05:00
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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2015-09-07 07:28:02 -04:00
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self.comb += [
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Record.connect(self.streamer.source, self.streamer_randomizer.sink),
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Record.connect(self.streamer_randomizer.source, self.core.sink),
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Record.connect(self.core.source, self.logger_randomizer.sink),
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Record.connect(self.logger_randomizer.source, self.logger.sink)
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]
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2015-11-13 08:47:57 -05:00
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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for i in range(8):
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packet = mac.MACPacket([i for i in range(64)])
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packet.target_mac = 0x010203040506
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packet.sender_mac = 0x090A0B0C0C0D
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packet.ethernet_type = 0x0800
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packet.encode_header()
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yield from self.streamer.send(packet)
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yield from self.logger.receive()
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# check results
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s, l, e = check(packet, self.logger.packet)
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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2015-09-07 07:28:02 -04:00
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if __name__ == "__main__":
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2015-11-13 08:47:57 -05:00
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run_simulation(TB(), ncycles=4000, vcd_name="my.vcd", keep_files=True)
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