frontend/etherbone: Switch to LiteXModule.
This commit is contained in:
Florent Kermarrec
parent
e7ea355959
commit
01bdf0de07
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@ -1,7 +1,7 @@
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2015-2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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"""
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@ -15,6 +15,8 @@ and introduces some limitations:
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- 1 record per frame
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"""
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from litex.gen import *
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from liteeth.common import *
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from litex.soc.interconnect import wishbone
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@ -29,17 +31,18 @@ class LiteEthEtherbonePacketPacketizer(Packetizer):
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Packetizer.__init__(self,
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eth_etherbone_packet_description(32),
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eth_udp_user_description(32),
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etherbone_packet_header)
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etherbone_packet_header
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)
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class LiteEthEtherbonePacketTX(Module):
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class LiteEthEtherbonePacketTX(LiteXModule):
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def __init__(self, udp_port):
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self.sink = sink = stream.Endpoint(eth_etherbone_packet_user_description(32))
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self.source = source = stream.Endpoint(eth_udp_user_description(32))
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# # #
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self.submodules.packetizer = packetizer = LiteEthEtherbonePacketPacketizer()
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self.packetizer = packetizer = LiteEthEtherbonePacketPacketizer()
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self.comb += [
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sink.connect(packetizer.sink, keep={"valid", "last", "last_be", "ready", "data"}),
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sink.connect(packetizer.sink, keep={"pf", "pr", "nr"}),
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@ -48,7 +51,7 @@ class LiteEthEtherbonePacketTX(Module):
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packetizer.sink.port_size.eq(32//8),
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packetizer.sink.addr_size.eq(32//8),
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(packetizer.source.valid,
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NextState("SEND")
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@ -74,17 +77,17 @@ class LiteEthEtherbonePacketDepacketizer(Depacketizer):
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etherbone_packet_header)
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class LiteEthEtherbonePacketRX(Module):
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class LiteEthEtherbonePacketRX(LiteXModule):
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def __init__(self):
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self.sink = sink = stream.Endpoint(eth_udp_user_description(32))
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self.source = source = stream.Endpoint(eth_etherbone_packet_user_description(32))
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# # #
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self.submodules.depacketizer = depacketizer = LiteEthEtherbonePacketDepacketizer()
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self.depacketizer = depacketizer = LiteEthEtherbonePacketDepacketizer()
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self.comb += sink.connect(depacketizer.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(depacketizer.source.valid,
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NextState("DROP"),
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@ -118,10 +121,10 @@ class LiteEthEtherbonePacketRX(Module):
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)
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class LiteEthEtherbonePacket(Module):
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class LiteEthEtherbonePacket(LiteXModule):
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def __init__(self, udp, udp_port, cd="sys"):
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self.submodules.tx = tx = LiteEthEtherbonePacketTX(udp_port)
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self.submodules.rx = rx = LiteEthEtherbonePacketRX()
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self.tx = tx = LiteEthEtherbonePacketTX(udp_port)
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self.rx = rx = LiteEthEtherbonePacketRX()
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udp_port = udp.crossbar.get_port(udp_port, dw=32, cd=cd)
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self.comb += [
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tx.source.connect(udp_port.sink),
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@ -132,21 +135,21 @@ class LiteEthEtherbonePacket(Module):
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# Etherbone Probe ----------------------------------------------------------------------------------
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class LiteEthEtherboneProbe(Module):
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class LiteEthEtherboneProbe(LiteXModule):
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def __init__(self):
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self.sink = sink = stream.Endpoint(eth_etherbone_packet_user_description(32))
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self.source = source = stream.Endpoint(eth_etherbone_packet_user_description(32))
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# # #
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self.submodules.fifo = fifo = PacketFIFO(eth_etherbone_packet_user_description(32),
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self.fifo = fifo = PacketFIFO(eth_etherbone_packet_user_description(32),
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payload_depth = 1,
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param_depth = 1,
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buffered = False
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)
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self.comb += sink.connect(fifo.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(fifo.source.valid,
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NextState("PROBE_RESPONSE")
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@ -181,7 +184,7 @@ class LiteEthEtherboneRecordDepacketizer(Depacketizer):
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etherbone_record_header)
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class LiteEthEtherboneRecordReceiver(Module):
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class LiteEthEtherboneRecordReceiver(LiteXModule):
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def __init__(self, buffer_depth=4):
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self.sink = sink = stream.Endpoint(eth_etherbone_record_description(32))
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self.source = source = stream.Endpoint(eth_etherbone_mmap_description(32))
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@ -189,7 +192,7 @@ class LiteEthEtherboneRecordReceiver(Module):
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# # #
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assert buffer_depth <= 256
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self.submodules.fifo = fifo = PacketFIFO(eth_etherbone_record_description(32),
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self.fifo = fifo = PacketFIFO(eth_etherbone_record_description(32),
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payload_depth = buffer_depth,
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param_depth = 1,
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buffered = True
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@ -202,7 +205,7 @@ class LiteEthEtherboneRecordReceiver(Module):
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count = Signal(max=512, reset_less=True)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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fifo.source.ready.eq(1),
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NextValue(count, 0),
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@ -260,7 +263,7 @@ class LiteEthEtherboneRecordReceiver(Module):
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)
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class LiteEthEtherboneRecordSender(Module):
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class LiteEthEtherboneRecordSender(LiteXModule):
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def __init__(self, buffer_depth=4):
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self.sink = sink = stream.Endpoint(eth_etherbone_mmap_description(32))
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self.source = source = stream.Endpoint(eth_etherbone_record_description(32))
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@ -268,14 +271,14 @@ class LiteEthEtherboneRecordSender(Module):
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# # #
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assert buffer_depth <= 256
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self.submodules.fifo = fifo = PacketFIFO(eth_etherbone_mmap_description(32),
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self.fifo = fifo = PacketFIFO(eth_etherbone_mmap_description(32),
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payload_depth = buffer_depth,
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param_depth = 1,
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buffered = True
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)
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self.comb += sink.connect(fifo.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(fifo.source.valid,
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NextState("SEND_BASE_ADDRESS")
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@ -311,7 +314,7 @@ class LiteEthEtherboneRecordSender(Module):
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)
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class LiteEthEtherboneRecord(Module):
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class LiteEthEtherboneRecord(LiteXModule):
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def __init__(self, endianness="big", buffer_depth=4):
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self.sink = sink = stream.Endpoint(eth_etherbone_packet_user_description(32))
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self.source = source = stream.Endpoint(eth_etherbone_packet_user_description(32))
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@ -319,8 +322,8 @@ class LiteEthEtherboneRecord(Module):
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# # #
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# Receive record, decode it and generate mmap stream
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self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
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self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver(buffer_depth)
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self.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
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self.receiver = receiver = LiteEthEtherboneRecordReceiver(buffer_depth)
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self.comb += [
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sink.connect(depacketizer.sink),
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depacketizer.source.connect(receiver.sink)
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@ -339,8 +342,8 @@ class LiteEthEtherboneRecord(Module):
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]
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# Receive MMAP stream, encode it and send records
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self.submodules.sender = sender = LiteEthEtherboneRecordSender(buffer_depth)
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self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
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self.sender = sender = LiteEthEtherboneRecordSender(buffer_depth)
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self.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
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self.comb += [
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sender.source.connect(packetizer.sink),
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packetizer.source.connect(source),
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@ -354,7 +357,7 @@ class LiteEthEtherboneRecord(Module):
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# Etherbone Wishbone Master ------------------------------------------------------------------------
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class LiteEthEtherboneWishboneMaster(Module):
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class LiteEthEtherboneWishboneMaster(LiteXModule):
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def __init__(self):
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self.sink = sink = stream.Endpoint(eth_etherbone_mmap_description(32))
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self.source = source = stream.Endpoint(eth_etherbone_mmap_description(32))
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@ -364,7 +367,7 @@ class LiteEthEtherboneWishboneMaster(Module):
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data_update = Signal()
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ready.eq(1),
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If(sink.valid,
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@ -422,7 +425,7 @@ class LiteEthEtherboneWishboneMaster(Module):
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# Etherbone Wishbone Slave -------------------------------------------------------------------------
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class LiteEthEtherboneWishboneSlave(Module):
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class LiteEthEtherboneWishboneSlave(LiteXModule):
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def __init__(self):
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self.bus = bus = wishbone.Interface()
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self.sink = sink = stream.Endpoint(eth_etherbone_mmap_description(32))
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@ -430,7 +433,7 @@ class LiteEthEtherboneWishboneSlave(Module):
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ready.eq(1),
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If(bus.stb & bus.cyc,
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@ -480,14 +483,14 @@ class LiteEthEtherboneWishboneSlave(Module):
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# Etherbone ----------------------------------------------------------------------------------------
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class LiteEthEtherbone(Module):
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class LiteEthEtherbone(LiteXModule):
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def __init__(self, udp, udp_port, mode="master", buffer_depth=4, cd="sys"):
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# Encode/encode etherbone packets
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self.submodules.packet = packet = LiteEthEtherbonePacket(udp, udp_port, cd)
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self.packet = packet = LiteEthEtherbonePacket(udp, udp_port, cd)
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# Packets can be probe (etherbone discovering) or records with writes and reads
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self.submodules.probe = probe = LiteEthEtherboneProbe()
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self.submodules.record = record = LiteEthEtherboneRecord(buffer_depth=buffer_depth)
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self.probe = probe = LiteEthEtherboneProbe()
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self.record = record = LiteEthEtherboneRecord(buffer_depth=buffer_depth)
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# Arbitrate/dispatch probe/records packets
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dispatcher = Dispatcher(packet.source, [probe.sink, record.sink])
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@ -496,7 +499,7 @@ class LiteEthEtherbone(Module):
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self.submodules += dispatcher, arbiter
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# Create MMAP wishbone
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self.submodules.wishbone = {
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self.wishbone = {
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"master": LiteEthEtherboneWishboneMaster(),
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"slave": LiteEthEtherboneWishboneSlave(),
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}[mode]
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