diff --git a/bench/xcu1525.py b/bench/xcu1525.py
index 6082481..d6575eb 100755
--- a/bench/xcu1525.py
+++ b/bench/xcu1525.py
@@ -73,7 +73,7 @@ class BenchSoC(SoCCore):
         self.submodules.ethphy = USP_1000BASEX(self.crg.cd_eth.clk,
             data_pads    = self.platform.request("qsfp", 0),
             sys_clk_freq = self.clk_freq)
-        #self.comb += self.platform.request("qsfp_fs").eq(0b01)
+        self.comb += self.platform.request("qsfp_fs").eq(0b01)
         self.add_etherbone(phy=self.ethphy, buffer_depth=255)
 
         # SRAM -------------------------------------------------------------------------------------
diff --git a/liteeth/phy/usp_1000basex.py b/liteeth/phy/usp_1000basex.py
index 904af2f..e6b5a05 100644
--- a/liteeth/phy/usp_1000basex.py
+++ b/liteeth/phy/usp_1000basex.py
@@ -113,7 +113,7 @@ class USP_1000BASEX(Module, AutoCSR):
             p_A_RXTERMINATION              = 0b1,
             p_A_TXDIFFCTRL                 = 0b01100,
             p_A_TXPROGDIVRESET             = 0b0,
-            p_CBCC_DATA_SOURCE_SEL         = "ENCODED",
+            p_CBCC_DATA_SOURCE_SEL         = "DECODED",
             p_CDR_SWAP_MODE_EN             = 0b0,
             p_CFOK_PWRSVE_EN               = 0b1,
             p_CHAN_BOND_KEEP_ALIGN         = "FALSE",
@@ -140,24 +140,24 @@ class USP_1000BASEX(Module, AutoCSR):
             p_CKCAL2_CFG_2                 = 0b0001000000000000,
             p_CKCAL2_CFG_3                 = 0b0000000000000000,
             p_CKCAL2_CFG_4                 = 0b0000000000000000,
-            p_CLK_CORRECT_USE              = "TRUE",
+            p_CLK_CORRECT_USE              = "FALSE",
             p_CLK_COR_KEEP_IDLE            = "FALSE",
-            p_CLK_COR_MAX_LAT              = 15,
-            p_CLK_COR_MIN_LAT              = 12,
+            p_CLK_COR_MAX_LAT              = 20,
+            p_CLK_COR_MIN_LAT              = 18,
             p_CLK_COR_PRECEDENCE           = "TRUE",
             p_CLK_COR_REPEAT_WAIT          = 0,
-            p_CLK_COR_SEQ_1_1              = 0b0010111100,
-            p_CLK_COR_SEQ_1_2              = 0b0001010000,
-            p_CLK_COR_SEQ_1_3              = 0b0000000000,
-            p_CLK_COR_SEQ_1_4              = 0b0000000000,
+            p_CLK_COR_SEQ_1_1              = 0b0100000000,
+            p_CLK_COR_SEQ_1_2              = 0b0100000000,
+            p_CLK_COR_SEQ_1_3              = 0b0100000000,
+            p_CLK_COR_SEQ_1_4              = 0b0100000000,
             p_CLK_COR_SEQ_1_ENABLE         = 0b1111,
-            p_CLK_COR_SEQ_2_1              = 0b0010111100,
-            p_CLK_COR_SEQ_2_2              = 0b0010110101,
+            p_CLK_COR_SEQ_2_1              = 0b0100000000,
+            p_CLK_COR_SEQ_2_2              = 0b0100000000,
             p_CLK_COR_SEQ_2_3              = 0b0100000000,
             p_CLK_COR_SEQ_2_4              = 0b0100000000,
             p_CLK_COR_SEQ_2_ENABLE         = 0b1111,
-            p_CLK_COR_SEQ_2_USE            = "TRUE",
-            p_CLK_COR_SEQ_LEN              = 2,
+            p_CLK_COR_SEQ_2_USE            = "FALSE",
+            p_CLK_COR_SEQ_LEN              = 1,
             p_CPLL_CFG0                    = 0b0000000111111010,
             p_CPLL_CFG1                    = 0b0000000000101011,
             p_CPLL_CFG2                    = 0b0000000000000010,
@@ -268,7 +268,7 @@ class USP_1000BASEX(Module, AutoCSR):
             p_RTX_BUF_CML_CTRL             = 0b011,
             p_RTX_BUF_TERM_CTRL            = 0b00,
             p_RXBUFRESET_TIME              = 0b00011,
-            p_RXBUF_ADDR_MODE              = "FULL",
+            p_RXBUF_ADDR_MODE              = "FAST",
             p_RXBUF_EIDLE_HI_CNT           = 0b1000,
             p_RXBUF_EIDLE_LO_CNT           = 0b0000,
             p_RXBUF_EN                     = "TRUE",
@@ -549,7 +549,7 @@ class USP_1000BASEX(Module, AutoCSR):
             p_TX_PMA_POWER_SAVE            = 0b0,
             p_TX_PMA_RSV0                  = 0b0000000000000000,
             p_TX_PMA_RSV1                  = 0b0000000000000000,
-            p_TX_PROGCLK_SEL               = "PREPI",
+            p_TX_PROGCLK_SEL               = "CPLL",
             p_TX_PROGDIV_CFG               = 20.0,
             p_TX_PROGDIV_RATE              = 0b0000000000000001,
             p_TX_RXDETECT_CFG              = 0b00000000110010,