From 6a9a5132f6d5bc83185cc4d38a108d939ccc1d83 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Sat, 22 Aug 2020 10:57:35 +0200 Subject: [PATCH] Update gen.py to work with latest LiteX in wishbone mode Previously, it would fail with: $ liteeth/gen.py examples/wishbone_mii.yml [snip] Traceback (most recent call last): File "liteeth/gen.py", line 346, in main() File "liteeth/gen.py", line 331, in main soc = MACCore(platform, core_config) File "liteeth/gen.py", line 244, in __init__ self.add_wb_master(bridge.wishbone) File "[...]/litex/soc/integration/soc_core.py", line 202, in add_wb_master self.bus.add_master(master=wbm) File "[...]/litex/soc/integration/soc.py", line 347, in add_master master = self.add_adapter(name, master, "m2s") File "[...]/litex/soc/integration/soc.py", line 316, in add_adapter bridge_cls = { KeyError: (, ) --- liteeth/gen.py | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index 97838fa..9db3398 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -234,14 +234,9 @@ class MACCore(PHYCore): self.add_csr("ethmac") # Wishbone Interface ----------------------------------------------------------------------- - class _WishboneBridge(Module): - def __init__(self, interface): - self.wishbone = interface - self.wishbone.data_width = 32 - - bridge = _WishboneBridge(self.platform.request("wishbone")) - self.submodules += bridge - self.add_wb_master(bridge.wishbone) + wb_bus = wishbone.Interface() + self.add_wb_master(wb_bus) + self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="slave") # Interrupt Interface ---------------------------------------------------------------------- self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq)