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phy/xgmii: Switch to LiteXModule and some cleanups.

This commit is contained in:
Florent Kermarrec 2024-07-10 11:56:08 +02:00
parent ec7320f003
commit 08c10774b5
1 changed files with 20 additions and 22 deletions
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42
liteeth/phy/xgmii.py
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@ -6,9 +6,6 @@
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
from functools import reduce from functools import reduce
from operator import or_
from migen import Module
from litex.gen import * from litex.gen import *
@ -22,7 +19,7 @@ XGMII_END = Constant(0xFD, bits_sign=8)
# LiteEth PHY XGMII TX ----------------------------------------------------------------------------- # LiteEth PHY XGMII TX -----------------------------------------------------------------------------
class LiteEthPHYXGMIITX(Module): class LiteEthPHYXGMIITX(LiteXModule):
def __init__(self, pads, dw, dic=True): def __init__(self, pads, dw, dic=True):
# Enforce 64-bit data path # Enforce 64-bit data path
assert dw == 64 assert dw == 64
@ -202,7 +199,7 @@ class LiteEthPHYXGMIITX(Module):
# ---------- XGMII transmission logic ---------- # ---------- XGMII transmission logic ----------
# Transmit FSM # Transmit FSM
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
# This block will be executed by the FSM below in the IDLE state, when # This block will be executed by the FSM below in the IDLE state, when
# it's time to start a transmission aligned on the FIRST byte in a # it's time to start a transmission aligned on the FIRST byte in a
@ -458,7 +455,7 @@ class LiteEthPHYXGMIITX(Module):
# LiteEth PHY XGMII RX Aligner --------------------------------------------------------------------- # LiteEth PHY XGMII RX Aligner ---------------------------------------------------------------------
class LiteEthPHYXGMIIRXAligner(Module): class LiteEthPHYXGMIIRXAligner(LiteXModule):
def __init__(self, unaligned_ctl, unaligned_data): def __init__(self, unaligned_ctl, unaligned_data):
# Aligned ctl and data characters # Aligned ctl and data characters
self.aligned_ctl = Signal.like(unaligned_ctl) self.aligned_ctl = Signal.like(unaligned_ctl)
@ -470,7 +467,7 @@ class LiteEthPHYXGMIIRXAligner(Module):
# Alignment FSM # Alignment FSM
self.submodules.fsm = fsm = FSM(reset_state="NOSHIFT") self.fsm = fsm = FSM(reset_state="NOSHIFT")
fsm.act("NOSHIFT", fsm.act("NOSHIFT",
If(unaligned_ctl[4] & (unaligned_data[4*8:5*8] == XGMII_START), If(unaligned_ctl[4] & (unaligned_data[4*8:5*8] == XGMII_START),
@ -529,7 +526,7 @@ class LiteEthPHYXGMIIRX(LiteXModule):
# XGMII bus word, which we can do without packet loss given 10G Ethernet # XGMII bus word, which we can do without packet loss given 10G Ethernet
# mandates a 5-byte interpacket gap (which may be less at the receiver, # mandates a 5-byte interpacket gap (which may be less at the receiver,
# but this assumption seems to work for now). # but this assumption seems to work for now).
self.submodules.aligner = LiteEthPHYXGMIIRXAligner(pads.rx_ctl, pads.rx_data) self.aligner = LiteEthPHYXGMIIRXAligner(pads.rx_ctl, pads.rx_data)
# We need to have a lookahead and buffer the XGMII bus to properly # We need to have a lookahead and buffer the XGMII bus to properly
# determine whether we are processing the last bus word in some # determine whether we are processing the last bus word in some
@ -583,7 +580,7 @@ class LiteEthPHYXGMIIRX(LiteXModule):
] ]
# Receive FSM # Receive FSM
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
# The Ethernet preamble and start of frame character must follow # The Ethernet preamble and start of frame character must follow
@ -639,11 +636,11 @@ class LiteEthPHYXGMIIRX(LiteXModule):
# LiteEth PHY XGMII CRG ---------------------------------------------------------------------------- # LiteEth PHY XGMII CRG ----------------------------------------------------------------------------
class LiteEthPHYXGMIICRG(Module, AutoCSR): class LiteEthPHYXGMIICRG(LiteXModule):
def __init__(self, clock_pads, model=False): def __init__(self, clock_pads, model=False):
self._reset = CSRStorage() self._reset = CSRStorage()
self.clock_domains.cd_eth_rx = ClockDomain() self.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain() self.cd_eth_tx = ClockDomain()
if model: if model:
self.comb += [ self.comb += [
self.cd_eth_rx.clk.eq(ClockSignal()), self.cd_eth_rx.clk.eq(ClockSignal()),
@ -657,7 +654,7 @@ class LiteEthPHYXGMIICRG(Module, AutoCSR):
# LiteEth PHY XGMII -------------------------------------------------------------------------------- # LiteEth PHY XGMII --------------------------------------------------------------------------------
class LiteEthPHYXGMII(Module, AutoCSR): class LiteEthPHYXGMII(LiteXModule):
dw = 8 dw = 8
tx_clk_freq = 156.25e6 tx_clk_freq = 156.25e6
rx_clk_freq = 156.25e6 rx_clk_freq = 156.25e6
@ -665,13 +662,14 @@ class LiteEthPHYXGMII(Module, AutoCSR):
self.dw = dw self.dw = dw
self.cd_eth_tx, self.cd_eth_rx = "eth_tx", "eth_rx" self.cd_eth_tx, self.cd_eth_rx = "eth_tx", "eth_rx"
self.integrated_ifg_inserter = True self.integrated_ifg_inserter = True
self.submodules.crg = LiteEthPHYXGMIICRG(clock_pads, model) self.crg = LiteEthPHYXGMIICRG(clock_pads, model)
self.submodules.tx = ClockDomainsRenamer(self.cd_eth_tx)( self.tx = ClockDomainsRenamer(self.cd_eth_tx)(LiteEthPHYXGMIITX(
LiteEthPHYXGMIITX( pads = pads,
pads, dw = self.dw,
self.dw, dic = dic,
dic=dic, ))
)) self.rx = ClockDomainsRenamer(self.cd_eth_rx)(LiteEthPHYXGMIIRX(
self.submodules.rx = ClockDomainsRenamer(self.cd_eth_rx)( pads = pads,
LiteEthPHYXGMIIRX(pads, self.dw)) dw = self.dw,
))
self.sink, self.source = self.tx.sink, self.rx.source self.sink, self.source = self.tx.sink, self.rx.source