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core/arp: Fix mem_wr_port alias direction.

This commit is contained in:
Florent Kermarrec 2023-10-13 14:31:03 +02:00
parent 9d13f612c1
commit 09d31b5af8
1 changed files with 3 additions and 3 deletions
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6
liteeth/core/arp.py
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@ -191,9 +191,9 @@ class LiteEthARPCache(LiteXModule):
mem_wr_port_ip_address = Signal(32) mem_wr_port_ip_address = Signal(32)
mem_wr_port_mac_address = Signal(48) mem_wr_port_mac_address = Signal(48)
self.comb += [ self.comb += [
mem_wr_port_valid.eq(mem_wr_port.dat_w[80]), mem_wr_port.dat_w[80].eq(mem_wr_port_valid),
mem_wr_port_ip_address.eq(mem_wr_port.dat_w[0:32]), mem_wr_port.dat_w[0:32].eq(mem_wr_port_ip_address),
mem_wr_port_mac_address.eq(mem_wr_port.dat_w[32:80]), mem_wr_port.dat_w[32:80].eq(mem_wr_port_mac_address),
] ]
# Memory rd_port aliases. # Memory rd_port aliases.