From 0a922bb2ad6b424f3d1f62cf6577cfa4b762be9b Mon Sep 17 00:00:00 2001 From: Vamsi K Vytla Date: Fri, 17 Jan 2020 09:23:03 -0800 Subject: [PATCH] A few minor changes that help RGMII phy related debugging. {s6, s7, us}rgmii.py Make dw a class variable instead --- liteeth/core/ip.py | 2 +- liteeth/phy/s6rgmii.py | 3 ++- liteeth/phy/s7rgmii.py | 7 ++++--- liteeth/phy/usrgmii.py | 3 ++- 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py index 22f2b18..4890628 100644 --- a/liteeth/core/ip.py +++ b/liteeth/core/ip.py @@ -208,7 +208,7 @@ class LiteEthIPRX(Module): NextState("CHECK") ) ) - valid = Signal(reset_less=True) + self.valid = valid = Signal(reset_less=True) self.sync += valid.eq( depacketizer.source.valid & (depacketizer.source.target_ip == ip_address) & diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index 7623548..387c804 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -246,8 +246,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR): + dw = 8 + def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): - self.dw = 8 self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay)) diff --git a/liteeth/phy/s7rgmii.py b/liteeth/phy/s7rgmii.py index 65b47fd..d9f925e 100644 --- a/liteeth/phy/s7rgmii.py +++ b/liteeth/phy/s7rgmii.py @@ -120,7 +120,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): tx_phase = 125e6*tx_delay*360 assert tx_phase < 360 - pll_locked = Signal() + self.pll_locked = pll_locked = Signal() pll_fb = Signal() pll_clk_tx = Signal() pll_clk_tx_delayed = Signal() @@ -153,7 +153,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): ] # Reset - reset = Signal() + self.reset = reset = Signal() if with_hw_init_reset: self.submodules.hw_reset = LiteEthPHYHWReset() self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) @@ -168,8 +168,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR): + dw = 8 + def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): - self.dw = 8 self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay)) diff --git a/liteeth/phy/usrgmii.py b/liteeth/phy/usrgmii.py index 179a483..ce5d661 100644 --- a/liteeth/phy/usrgmii.py +++ b/liteeth/phy/usrgmii.py @@ -214,8 +214,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR): + dw = 8 + def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): - self.dw = 8 self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay))