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setup.py: Improve indentation.

This commit is contained in:
Florent Kermarrec 2023-12-19 09:10:32 +01:00
parent 4eec8419d0
commit 0ae737956d
1 changed files with 25 additions and 29 deletions
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42
setup.py
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@ -9,28 +9,24 @@ with open("README.md", "r") as fp:
setup(
name="liteeth",
version="2023.08",
description="Small footprint and configurable Ethernet core",
long_description=long_description,
long_description_content_type="text/markdown",
author="Florent Kermarrec",
author_email="florent@enjoy-digital.fr",
url="http://enjoy-digital.fr",
download_url="https://github.com/enjoy-digital/liteeth",
test_suite="test",
license="BSD",
python_requires="~=3.6",
install_requires=["pyyaml", "litex", "liteiclink"],
extras_require={
"develop": [
"setuptools"
]
},
packages=find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
include_package_data=True,
keywords="HDL ASIC FPGA hardware design",
classifiers=[
name = "liteeth",
version = "2023.08",
description = "Small footprint and configurable Ethernet core",
long_description = long_description,
long_description_content_type = "text/markdown",
author = "Florent Kermarrec",
author_email = "florent@enjoy-digital.fr",
url = "http://enjoy-digital.fr",
download_url = "https://github.com/enjoy-digital/liteeth",
test_suite = "test",
license = "BSD",
python_requires = "~=3.6",
install_requires = ["pyyaml", "litex", "liteiclink"],
extras_require = {"develop": ["setuptools"]},
packages = find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
include_package_data = True,
keywords = "HDL ASIC FPGA hardware design",
classifiers = [
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
"Environment :: Console",
"Development Status :: 3 - Alpha",
@ -39,7 +35,7 @@ setup(
"Operating System :: OS Independent",
"Programming Language :: Python",
],
entry_points={
entry_points = {
"console_scripts": [
"liteeth_gen=liteeth.gen:main",
],