test/test_mac_wishbone: Update with TX/RX slot changes.
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@ -102,12 +102,13 @@ class DUT(Module):
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def main_generator(dut):
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def main_generator(dut):
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wishbone_master = WishboneMaster(dut.ethmac.bus)
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wishbone_tx_master = WishboneMaster(dut.ethmac.bus_tx)
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wishbone_rx_master = WishboneMaster(dut.ethmac.bus_rx)
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sram_reader_driver = SRAMReaderDriver(dut.ethmac.interface.sram.reader)
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sram_reader_driver = SRAMReaderDriver(dut.ethmac.interface.sram.reader)
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sram_writer_driver = SRAMWriterDriver(dut.ethmac.interface.sram.writer)
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sram_writer_driver = SRAMWriterDriver(dut.ethmac.interface.sram.writer)
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sram_writer_slots_offset = [0x000, 0x200]
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sram_writer_slots_offset = [0x000, 0x200]
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sram_reader_slots_offset = [0x400, 0x600]
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sram_reader_slots_offset = [0x000, 0x200]
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length = 150+2
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length = 150+2
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@ -121,7 +122,7 @@ def main_generator(dut):
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# fill tx memory
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# fill tx memory
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for i in range(length//4+1):
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for i in range(length//4+1):
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dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")
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dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")
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yield from wishbone_master.write(sram_reader_slots_offset[slot]+i, dat)
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yield from wishbone_tx_master.write(sram_reader_slots_offset[slot]+i, dat)
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# send tx payload & wait
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# send tx payload & wait
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yield from sram_reader_driver.start(slot, length)
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yield from sram_reader_driver.start(slot, length)
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@ -135,8 +136,8 @@ def main_generator(dut):
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# get rx payload (loopback on PHY Model)
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# get rx payload (loopback on PHY Model)
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rx_payload = []
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rx_payload = []
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for i in range(length//4+1):
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for i in range(length//4+1):
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yield from wishbone_master.read(sram_writer_slots_offset[slot]+i)
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yield from wishbone_tx_master.read(sram_writer_slots_offset[slot]+i)
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dat = wishbone_master.dat
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dat = wishbone_tx_master.dat
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rx_payload += list(dat.to_bytes(4, byteorder='big'))
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rx_payload += list(dat.to_bytes(4, byteorder='big'))
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# check results
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# check results
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