From 0e8079a9da90689eeb50ae381d6d1a65c842a0e8 Mon Sep 17 00:00:00 2001
From: Andrei Novysh <andrei.novysh@gmail.com>
Date: Sun, 14 Apr 2024 00:37:31 +0300
Subject: [PATCH] phy/ecp5rgmii.py: In-Band Status CSRField("clock_speed") size
 fixed

---
 liteeth/phy/ecp5rgmii.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/liteeth/phy/ecp5rgmii.py b/liteeth/phy/ecp5rgmii.py
index 4af82c5..27192a1 100644
--- a/liteeth/phy/ecp5rgmii.py
+++ b/liteeth/phy/ecp5rgmii.py
@@ -71,7 +71,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
                     ("``0b0``", "Link down."),
                     ("``0b1``", "Link up."),
                 ]),
-                CSRField("clock_speed", size=1, values=[
+                CSRField("clock_speed", size=2, values=[
                     ("``0b00``", "2.5MHz   (10Mbps)."),
                     ("``0b01``", "25MHz   (100MBps)."),
                     ("``0b10``", "125MHz (1000MBps)."),