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phy/efinix: IO exclusion on DDROutput/Input now directly done in LiteX.

This commit is contained in:
Florent Kermarrec 2023-08-30 18:09:41 +02:00
parent 8436d775f6
commit 0f055b1c0f
2 changed files with 0 additions and 12 deletions
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6
liteeth/phy/titaniumrgmii.py
View File

@ -38,8 +38,6 @@ class LiteEthPHYRGMIITX(LiteXModule):
o = pads.tx_data[n],
clk = "auto_eth_tx_clk", # FIXME.
)
# FIXME: Integrate in EfinixDDROutputImpl.
platform.toolchain.excluded_ios.append(pads.tx_data)
# TX Ctl IOs.
# -----------
@ -52,8 +50,6 @@ class LiteEthPHYRGMIITX(LiteXModule):
o = pads.tx_ctl,
clk = "auto_eth_tx_clk", # FIXME.
)
# FIXME: Integrate in EfinixDDROutputImpl.
platform.toolchain.excluded_ios.append(pads.tx_ctl)
else:
self.sync.eth_tx += pads.tx_ctl.eq(sink.valid)
@ -90,8 +86,6 @@ class LiteEthPHYRGMIIRX(LiteXModule):
o2 = rx_data_l[n],
clk = "auto_eth_rx_clk", # FIXME.
)
# FIXME: Integrate in EfinixDDROutputImpl.
platform.toolchain.excluded_ios.append(pads.rx_data)
# RX Ctl IOs.
# -----------

6
liteeth/phy/trionrgmii.py
View File

@ -38,8 +38,6 @@ class LiteEthPHYRGMIITX(LiteXModule):
o = pads.tx_data[n],
clk = "auto_eth_tx_clk", # FIXME.
)
# FIXME: Integrate in EfinixDDROutputImpl.
platform.toolchain.excluded_ios.append(pads.tx_data)
# TX Ctl IOs.
# -----------
@ -52,8 +50,6 @@ class LiteEthPHYRGMIITX(LiteXModule):
o = pads.tx_ctl,
clk = "auto_eth_tx_clk", # FIXME.
)
# FIXME: Integrate in EfinixDDROutputImpl.
platform.toolchain.excluded_ios.append(pads.tx_ctl)
else:
self.sync.eth_tx += pads.tx_ctl.eq(sink.valid)
@ -90,8 +86,6 @@ class LiteEthPHYRGMIIRX(LiteXModule):
o2 = rx_data_l[n],
clk = "auto_eth_rx_clk", # FIXME.
)
# FIXME: Integrate in EfinixDDROutputImpl.
platform.toolchain.excluded_ios.append(pads.rx_data)
# RX Ctl IOs.
# -----------