From 153c1606706dc7d8335e5b6ae670d2da66d34309 Mon Sep 17 00:00:00 2001
From: Xiretza <xiretza@xiretza.xyz>
Date: Tue, 11 Feb 2020 17:09:36 +0100
Subject: [PATCH] Prioritise overridden interrupts and memory regions

---
 liteeth/gen.py | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/liteeth/gen.py b/liteeth/gen.py
index dcfff04..7a9af3b 100644
--- a/liteeth/gen.py
+++ b/liteeth/gen.py
@@ -198,15 +198,15 @@ class PHYCore(SoCMini):
 # MAC Core -----------------------------------------------------------------------------------------
 
 class MACCore(PHYCore):
-    interrupt_map = {
+    interrupt_map = SoCCore.interrupt_map
+    interrupt_map.update({
         "ethmac": 2,
-    }
-    interrupt_map.update(SoCCore.interrupt_map)
+    })
 
-    mem_map = {
+    mem_map = SoCCore.mem_map
+    mem_map.update({
         "ethmac": 0x50000000
-    }
-    mem_map.update(SoCCore.mem_map)
+    })
 
     def __init__(self, phy, clk_freq, endianness):
         PHYCore.__init__(self, phy, clk_freq)