From 155be56f9c62ecfd9205a423acf237800d963583 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 17 Nov 2015 00:16:39 +0100 Subject: [PATCH] test: use new RemoteClient/RemoveServer provided by LiteX --- README | 4 +- example_designs/test/make.py | 36 --------- example_designs/test/test_etherbone.py | 82 ++++++++------------- example_designs/test/test_logic_analyzer.py | 36 ++++----- example_designs/test/test_regs.py | 32 +++++--- example_designs/test/test_tty.py | 9 ++- example_designs/test/test_udp.py | 8 +- 7 files changed, 82 insertions(+), 125 deletions(-) delete mode 100644 example_designs/test/make.py diff --git a/README b/README index d4d9d2b..806de0e 100644 --- a/README +++ b/README @@ -76,7 +76,7 @@ devel [AT] lists.m-labs.hk. 4. Test design (only for KC705 for now): try to ping 192.168.0.42 go to example_designs/test/ - run ./make.py test_udp + run ./test_udp.py 5. Build and load Etherbone design (only for KC705 for now): python3 make.py -t etherbone all load-bitstream @@ -84,7 +84,7 @@ devel [AT] lists.m-labs.hk. 6. Test design (only for KC705 for now): try to ping 192.168.0.42 go to example_designs/test/ - run ./make.py test_etherbone + run ./test_etherbone.py [> Simulations --------------- diff --git a/example_designs/test/make.py b/example_designs/test/make.py deleted file mode 100644 index 9e576a2..0000000 --- a/example_designs/test/make.py +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env python3 -import argparse -import importlib - - -def _get_args(): - parser = argparse.ArgumentParser() - parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use") - parser.add_argument("--port", default="2", help="UART port") - parser.add_argument("--baudrate", default=115200, help="UART baudrate") - parser.add_argument("--ip_address", default="192.168.0.42", help="Etherbone IP address") - parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port") - parser.add_argument("--busword", default=32, help="CSR busword") - - parser.add_argument("test", nargs="+", help="specify a test") - - return parser.parse_args() - -if __name__ == "__main__": - args = _get_args() - if args.bridge == "uart": - from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver - port = args.port if not args.port.isdigit() else int(args.port) - wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False) - elif args.bridge == "etherbone": - from liteeth.software.wishbone import LiteEthWishboneBridgeDriver - wb = LiteEthWishboneBridgeDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False) - else: - ValueError("Invalid bridge {}".format(args.bridge)) - - def _import(name): - return importlib.import_module(name) - - for test in args.test: - t = _import(test) - t.main(wb) diff --git a/example_designs/test/test_etherbone.py b/example_designs/test/test_etherbone.py index c06331f..e7d2bc5 100644 --- a/example_designs/test/test_etherbone.py +++ b/example_designs/test/test_etherbone.py @@ -1,62 +1,40 @@ import socket import time -from liteeth.software.etherbone import * +from litex.soc.tools.remote.etherbone import * SRAM_BASE = 0x02000000 -import socket +socket = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) +# test probe +packet = EtherbonePacket() +packet.pf = 1 +packet.encode() +socket.sendto(bytes(packet), ("192.168.0.42", 20000)) +time.sleep(0.01) -def main(wb): - sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) +# test writes +writes_datas = [j for j in range(16)] +writes = EtherboneWrites(base_addr=SRAM_BASE, datas=writes_datas) +record = EtherboneRecord() +record.writes = writes +record.wcount = len(writes_datas) - # test probe - packet = EtherbonePacket() - packet.pf = 1 - packet.encode() - sock.sendto(bytes(packet), ("192.168.0.42", 20000)) - time.sleep(0.01) +packet = EtherbonePacket() +packet.records = [record] +packet.encode() +socket.sendto(bytes(packet), ("192.168.0.42", 20000)) +time.sleep(0.01) - # test writes - writes_datas = [j for j in range(16)] - writes = EtherboneWrites(base_addr=SRAM_BASE, datas=writes_datas) - record = EtherboneRecord() - record.writes = writes - record.reads = None - record.bca = 0 - record.rca = 0 - record.rff = 0 - record.cyc = 0 - record.wca = 0 - record.wff = 0 - record.byte_enable = 0xf - record.wcount = len(writes_datas) - record.rcount = 0 +# test reads +reads_addrs = [SRAM_BASE+4*j for j in range(16)] +reads = EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs) +record = EtherboneRecord() +record.reads = reads +record.rcount = len(reads_addrs) - packet = EtherbonePacket() - packet.records = [record] - packet.encode() - sock.sendto(bytes(packet), ("192.168.0.42", 20000)) - time.sleep(0.01) - - # test reads - reads_addrs = [SRAM_BASE+4*j for j in range(16)] - reads = EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs) - record = EtherboneRecord() - record.writes = None - record.reads = reads - record.bca = 0 - record.rca = 0 - record.rff = 0 - record.cyc = 0 - record.wca = 0 - record.wff = 0 - record.byte_enable = 0xf - record.wcount = 0 - record.rcount = len(reads_addrs) - - packet = EtherbonePacket() - packet.records = [record] - packet.encode() - sock.sendto(bytes(packet), ("192.168.0.42", 20000)) - time.sleep(0.01) +packet = EtherbonePacket() +packet.records = [record] +packet.encode() +socket.sendto(bytes(packet), ("192.168.0.42", 20000)) +time.sleep(0.01) diff --git a/example_designs/test/test_logic_analyzer.py b/example_designs/test/test_logic_analyzer.py index fde48bc..0589fa3 100644 --- a/example_designs/test/test_logic_analyzer.py +++ b/example_designs/test/test_logic_analyzer.py @@ -1,23 +1,25 @@ import time -from litescope.software.driver.logic_analyzer import LiteScopeLogicAnalyzerDriver +from litex.soc.tools.remote import RemoteClient -def main(wb): - logic_analyzer = LiteScopeLogicAnalyzerDriver(wb.regs, "logic_analyzer", debug=True) +wb = RemoteClient() +wb.open() - wb.open() - regs = wb.regs - # # # - conditions = {} - logic_analyzer.configure_term(port=0, cond=conditions) - logic_analyzer.configure_sum("term") - # Run Logic Analyzer - logic_analyzer.run(offset=2048, length=4000) +logic_analyzer = LiteScopeLogicAnalyzerDriver(wb.regs, "logic_analyzer", debug=True) - while not logic_analyzer.done(): - pass +# # # +conditions = {} +logic_analyzer.configure_term(port=0, cond=conditions) +logic_analyzer.configure_sum("term") +# run logic analyzer +logic_analyzer.run(offset=2048, length=4000) - logic_analyzer.upload() - logic_analyzer.save("dump.vcd") - # # # - wb.close() +while not logic_analyzer.done(): + pass + +logic_analyzer.upload() +logic_analyzer.save("dump.vcd") + +# # # + +wb.close() diff --git a/example_designs/test/test_regs.py b/example_designs/test/test_regs.py index 44f6700..a9287c9 100644 --- a/example_designs/test/test_regs.py +++ b/example_designs/test/test_regs.py @@ -1,12 +1,20 @@ -def main(wb): - wb.open() - regs = wb.regs - # # # - print("sysid : 0x{:04x}".format(regs.identifier_sysid.read())) - print("revision : 0x{:04x}".format(regs.identifier_revision.read())) - print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000))) - SRAM_BASE = 0x02000000 - wb.write(SRAM_BASE, [i for i in range(64)]) - print(wb.read(SRAM_BASE, 64)) - # # # - wb.close() +from litex.soc.tools.remote import RemoteClient + +wb = RemoteClient() +wb.open() + +# # # + +identifier = "" +for i in range(30): + identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1? +print(identifier) +print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000)) + +SRAM_BASE = 0x02000000 +wb.write(SRAM_BASE, [i for i in range(64)]) +print(wb.read(SRAM_BASE, 64)) + +# # # + +wb.close() diff --git a/example_designs/test/test_tty.py b/example_designs/test/test_tty.py index fdf1d03..759e589 100644 --- a/example_designs/test/test_tty.py +++ b/example_designs/test/test_tty.py @@ -33,6 +33,9 @@ def test(fpga_ip, udp_port, test_message): pass -def main(wb): - test_message = "LiteEth virtual TTY Hello world\n" - test("192.168.0.42", 10000, test_message) +# # # + +test_message = "LiteEth virtual TTY Hello world\n" +test("192.168.0.42", 10000, test_message) + +# # # \ No newline at end of file diff --git a/example_designs/test/test_udp.py b/example_designs/test/test_udp.py index 6e98d07..9f8d13b 100644 --- a/example_designs/test/test_udp.py +++ b/example_designs/test/test_udp.py @@ -80,7 +80,9 @@ def test(fpga_ip, udp_port, test_size): except KeyboardInterrupt: pass +# # # -def main(wb): - test("192.168.0.42", 6000, 128*KB) - test("192.168.0.42", 8000, 128*KB) +test("192.168.0.42", 6000, 128*KB) +test("192.168.0.42", 8000, 128*KB) + +# # # \ No newline at end of file