diff --git a/liteeth/phy/pcs_1000basex.py b/liteeth/phy/pcs_1000basex.py
index e9d4cf5..ca71216 100644
--- a/liteeth/phy/pcs_1000basex.py
+++ b/liteeth/phy/pcs_1000basex.py
@@ -19,7 +19,7 @@ from litex.soc.cores.code_8b10b import K, D, Encoder, Decoder
 
 from liteeth.common import *
 
-# Constants / Helpers ------------------------------------------------------------------------------
+# PCS Constants / Helpers --------------------------------------------------------------------------
 
 SGMII_1000MBPS_SPEED = 0b10
 SGMII_100MBPS_SPEED  = 0b01
@@ -31,6 +31,35 @@ CTYPE_C2 = 0b1
 ITYPE_I1 = 0b0
 ITYPË_I2 = 0b1
 
+# PCS Gearbox --------------------------------------------------------------------------------------
+
+class PCSGearbox(LiteXModule):
+    def __init__(self):
+        self.tx_data      = Signal(10)
+        self.tx_data_half = Signal(20)
+        self.rx_data_half = Signal(20)
+        self.rx_data      = Signal(10)
+
+        # # #
+
+        # TX
+        buf = Signal(20)
+        self.sync.eth_tx += buf.eq(Cat(buf[10:], self.tx_data))
+        self.sync.eth_tx_half += self.tx_data_half.eq(buf)
+
+        # RX
+        phase_half       = Signal()
+        phase_half_rereg = Signal()
+        self.sync.eth_rx_half += phase_half_rereg.eq(phase_half)
+        self.sync.eth_rx += [
+            If(phase_half == phase_half_rereg,
+                self.rx_data.eq(self.rx_data_half[10:])
+            ).Else(
+                self.rx_data.eq(self.rx_data_half[:10])
+            ),
+            phase_half.eq(~phase_half),
+        ]
+
 # PCS TX -------------------------------------------------------------------------------------------
 
 class PCSTX(LiteXModule):
@@ -248,35 +277,6 @@ class PCSRX(LiteXModule):
             )
         )
 
-# PCS Gearbox --------------------------------------------------------------------------------------
-
-class PCSGearbox(LiteXModule):
-    def __init__(self):
-        self.tx_data      = Signal(10)
-        self.tx_data_half = Signal(20)
-        self.rx_data_half = Signal(20)
-        self.rx_data      = Signal(10)
-
-        # # #
-
-        # TX
-        buf = Signal(20)
-        self.sync.eth_tx += buf.eq(Cat(buf[10:], self.tx_data))
-        self.sync.eth_tx_half += self.tx_data_half.eq(buf)
-
-        # RX
-        phase_half       = Signal()
-        phase_half_rereg = Signal()
-        self.sync.eth_rx_half += phase_half_rereg.eq(phase_half)
-        self.sync.eth_rx += [
-            If(phase_half == phase_half_rereg,
-                self.rx_data.eq(self.rx_data_half[10:])
-            ).Else(
-                self.rx_data.eq(self.rx_data_half[:10])
-            ),
-            phase_half.eq(~phase_half),
-        ]
-
 # PCS ----------------------------------------------------------------------------------------------
 
 class PCS(LiteXModule):