Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

liteeth/phy/rmii: Replace MuliReg with stream.Delay.

This commit is contained in:
Florent Kermarrec 2024-09-23 11:05:23 +02:00
parent af746ec973
commit 1c89387d09
1 changed files with 6 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
liteeth/phy/rmii.py
View File

@ -49,13 +49,8 @@ class LiteEthPHYRMIIRX(LiteXModule):
converter = ResetInserter()(converter) converter = ResetInserter()(converter)
self.converter = converter self.converter = converter
converter_sink_valid = Signal() self.delay = delay = stream.Delay(layout=[("data", 8)], n=2)
converter_sink_data = Signal(2) self.comb += delay.source.connect(converter.sink)
self.specials += [
MultiReg(converter_sink_valid, converter.sink.valid, n=2),
MultiReg(converter_sink_data, converter.sink.data, n=2)
]
crs_dv = Signal() crs_dv = Signal()
crs_dv_d = Signal() crs_dv_d = Signal()
@ -69,16 +64,16 @@ class LiteEthPHYRMIIRX(LiteXModule):
self.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
If(crs_dv & (rx_data != 0b00), If(crs_dv & (rx_data != 0b00),
converter_sink_valid.eq(1), delay.sink.valid.eq(1),
converter_sink_data.eq(rx_data), delay.sink.data.eq(rx_data),
NextState("RECEIVE") NextState("RECEIVE")
).Else( ).Else(
converter.reset.eq(1) converter.reset.eq(1)
) )
) )
fsm.act("RECEIVE", fsm.act("RECEIVE",
converter_sink_valid.eq(1), delay.sink.valid.eq(1),
converter_sink_data.eq(rx_data), delay.sink.data.eq(rx_data),
# End of frame when 2 consecutives 0 on crs_dv. # End of frame when 2 consecutives 0 on crs_dv.
If(~(crs_dv | crs_dv_d), If(~(crs_dv | crs_dv_d),
converter.sink.last.eq(1), converter.sink.last.eq(1),