From 1d19de09ef78a908cb2dee9a3037cc1229738501 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 23 Sep 2024 15:30:08 +0200 Subject: [PATCH] phy/rmii: Cosmetic cleanups. --- liteeth/phy/rmii.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index 48d9c36..64c9e4f 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -107,8 +107,8 @@ class LiteEthPHYRMIICRG(LiteXModule): # # # - # RX/TX clocks - + # RX/TX clocks. + # ------------- self.cd_eth_rx = ClockDomain() self.cd_eth_tx = ClockDomain() @@ -129,7 +129,8 @@ class LiteEthPHYRMIICRG(LiteXModule): else: self.comb += clock_pads.ref_clk.eq(~clk_signal) # CHEKCME: Keep Invert? - # Reset + # Reset. + # ------ self.reset = reset = Signal() if with_hw_init_reset: self.hw_reset = LiteEthPHYHWReset() @@ -153,13 +154,21 @@ class LiteEthPHYRMII(LiteXModule): def __init__(self, clock_pads, pads, refclk_cd="eth", with_hw_init_reset = True, with_refclk_ddr_output = True): + + # CRG. + # ---- self.crg = LiteEthPHYRMIICRG(clock_pads, pads, refclk_cd, with_hw_init_reset = with_hw_init_reset, with_refclk_ddr_output = with_refclk_ddr_output, ) + + # TX/RX. + # ------ self.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads)) self.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads)) self.sink, self.source = self.tx.sink, self.rx.source + # MDIO. + # ----- if hasattr(pads, "mdc"): self.mdio = LiteEthPHYMDIO(pads)