phy/rmii: Cosmetic cleanups.
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f252eed154
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1d19de09ef
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@ -107,8 +107,8 @@ class LiteEthPHYRMIICRG(LiteXModule):
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# # #
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# # #
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# RX/TX clocks
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# RX/TX clocks.
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# -------------
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self.cd_eth_rx = ClockDomain()
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self.cd_eth_rx = ClockDomain()
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self.cd_eth_tx = ClockDomain()
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self.cd_eth_tx = ClockDomain()
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@ -129,7 +129,8 @@ class LiteEthPHYRMIICRG(LiteXModule):
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else:
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else:
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self.comb += clock_pads.ref_clk.eq(~clk_signal) # CHEKCME: Keep Invert?
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self.comb += clock_pads.ref_clk.eq(~clk_signal) # CHEKCME: Keep Invert?
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# Reset
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# Reset.
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# ------
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self.reset = reset = Signal()
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self.reset = reset = Signal()
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if with_hw_init_reset:
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if with_hw_init_reset:
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self.hw_reset = LiteEthPHYHWReset()
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self.hw_reset = LiteEthPHYHWReset()
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@ -153,13 +154,21 @@ class LiteEthPHYRMII(LiteXModule):
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def __init__(self, clock_pads, pads, refclk_cd="eth",
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def __init__(self, clock_pads, pads, refclk_cd="eth",
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with_hw_init_reset = True,
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with_hw_init_reset = True,
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with_refclk_ddr_output = True):
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with_refclk_ddr_output = True):
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# CRG.
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# ----
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self.crg = LiteEthPHYRMIICRG(clock_pads, pads, refclk_cd,
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self.crg = LiteEthPHYRMIICRG(clock_pads, pads, refclk_cd,
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with_hw_init_reset = with_hw_init_reset,
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with_hw_init_reset = with_hw_init_reset,
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with_refclk_ddr_output = with_refclk_ddr_output,
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with_refclk_ddr_output = with_refclk_ddr_output,
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)
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)
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# TX/RX.
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# ------
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self.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads))
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self.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads))
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self.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads))
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self.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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self.sink, self.source = self.tx.sink, self.rx.source
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# MDIO.
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# -----
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if hasattr(pads, "mdc"):
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if hasattr(pads, "mdc"):
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self.mdio = LiteEthPHYMDIO(pads)
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self.mdio = LiteEthPHYMDIO(pads)
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