From 1f19518d63b7954153f38ee5fbb4820dd8fd8679 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 9 Dec 2015 16:57:02 +0100 Subject: [PATCH] phy/common: add LiteEthPHYHWReset and use it on phys --- liteeth/phy/common.py | 16 ++++++++++++++++ liteeth/phy/gmii.py | 18 ++++++------------ liteeth/phy/mii.py | 18 ++++++------------ liteeth/phy/rmii.py | 18 ++++++------------ liteeth/phy/s6rgmii.py | 18 ++++++------------ liteeth/phy/s7rgmii.py | 18 ++++++------------ 6 files changed, 46 insertions(+), 60 deletions(-) diff --git a/liteeth/phy/common.py b/liteeth/phy/common.py index fbb1d85..9268fba 100644 --- a/liteeth/phy/common.py +++ b/liteeth/phy/common.py @@ -3,6 +3,22 @@ from liteeth.common import * from litex.gen.genlib.cdc import MultiReg from litex.gen.fhdl.specials import Tristate +class LiteEthPHYHWReset(Module): + def __init__(self): + self.reset = Signal() + + # # # + + counter = Signal(max=512) + counter_done = Signal() + counter_ce = Signal() + self.sync += If(counter_ce, counter.eq(counter + 1)) + self.comb += [ + counter_done.eq(counter == 256), + counter_ce.eq(~counter_done), + self.reset.eq(~counter_done) + ] + class LiteEthPHYMDIO(Module, AutoCSR): def __init__(self, pads): diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index f5fadf8..908c331 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -3,7 +3,7 @@ from liteeth.common import * from litex.gen.genlib.io import DDROutput from litex.gen.genlib.resetsync import AsyncResetSynchronizer -from liteeth.phy.common import LiteEthPHYMDIO +from liteeth.phy.common import * class LiteEthPHYGMIITX(Module): @@ -73,19 +73,13 @@ class LiteEthPHYGMIICRG(Module, AutoCSR): i_S=mii_mode, o_O=self.cd_eth_tx.clk) + reset = Signal() if with_hw_init_reset: - reset = Signal() - counter = Signal(max=512) - counter_done = Signal() - counter_ce = Signal() - self.sync += If(counter_ce, counter.eq(counter + 1)) - self.comb += [ - counter_done.eq(counter == 256), - counter_ce.eq(~counter_done), - reset.eq(~counter_done | self._reset.storage) - ] + self.submodules.hw_reset = LiteEthPHYHWReset() + self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: - reset = self._reset.storage + self.comb += reset.eq(self._reset.storage) + self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset), diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py index 3fd2de8..ce49a8a 100644 --- a/liteeth/phy/mii.py +++ b/liteeth/phy/mii.py @@ -2,7 +2,7 @@ from liteeth.common import * from litex.gen.genlib.resetsync import AsyncResetSynchronizer -from liteeth.phy.common import LiteEthPHYMDIO +from liteeth.phy.common import * def converter_description(dw): @@ -83,19 +83,13 @@ class LiteEthPHYMIICRG(Module, AutoCSR): self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx) self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx) + reset = Signal() if with_hw_init_reset: - reset = Signal() - counter_done = Signal() - counter = Signal(max=512) - counter_ce = Signal() - self.sync += If(counter_ce, counter.eq(counter + 1)) - self.comb += [ - counter_done.eq(counter == 256), - counter_ce.eq(~counter_done), - reset.eq(~counter_done | self._reset.storage) - ] + self.submodules.hw_reset = LiteEthPHYHWReset() + self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: - reset = self._reset.storage + self.comb += reset.eq(self._reset.storage) + self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset), diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index 92da7be..71e32f3 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -5,7 +5,7 @@ from litex.gen.genlib.misc import WaitTimer from litex.gen.genlib.io import DDROutput from litex.gen.genlib.resetsync import AsyncResetSynchronizer -from liteeth.phy.common import LiteEthPHYMDIO +from liteeth.phy.common import * def converter_description(dw): @@ -107,19 +107,13 @@ class LiteEthPHYRMIICRG(Module, AutoCSR): self.specials += DDROutput(0, 1, clock_pads.ref_clk, ClockSignal("eth_tx")) + reset = Signal() if with_hw_init_reset: - reset = Signal() - counter_done = Signal() - counter = Signal(max=512) - counter_ce = Signal() - self.sync += If(counter_ce, counter.eq(counter + 1)) - self.comb += [ - counter_done.eq(counter == 256), - counter_ce.eq(~counter_done), - reset.eq(~counter_done | self._reset.storage) - ] + self.submodules.hw_reset = LiteEthPHYHWReset() + self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: - reset = self._reset.storage + self.comb += reset.eq(self._reset.storage) + self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset), diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index 744369d..b2e5206 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -7,7 +7,7 @@ from litex.gen.genlib.fsm import FSM, NextState from litex.gen.genlib.resetsync import AsyncResetSynchronizer -from liteeth.phy.common import LiteEthPHYMDIO +from liteeth.phy.common import * class LiteEthPHYRGMIITX(Module): @@ -134,19 +134,13 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): self.specials += Instance("BUFG", i_I=self.cd_eth_rx.clk, o_O=self.cd_eth_tx.clk) # Reset + reset = Signal() if with_hw_init_reset: - reset = Signal() - counter_done = Signal() - counter = Signal(max=512) - counter_ce = Signal() - self.sync += If(counter_ce, counter.eq(counter + 1)) - self.comb += [ - counter_done.eq(counter == 256), - counter_ce.eq(~counter_done), - reset.eq(~counter_done | self._reset.storage) - ] + self.submodules.hw_reset = LiteEthPHYHWReset() + self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: - reset = self._reset.storage + self.comb += reset.eq(self._reset.storage) + self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset), diff --git a/liteeth/phy/s7rgmii.py b/liteeth/phy/s7rgmii.py index 9e4446f..b82fbf3 100644 --- a/liteeth/phy/s7rgmii.py +++ b/liteeth/phy/s7rgmii.py @@ -7,7 +7,7 @@ from litex.gen.genlib.fsm import FSM, NextState from litex.gen.genlib.resetsync import AsyncResetSynchronizer -from liteeth.phy.common import LiteEthPHYMDIO +from liteeth.phy.common import * class LiteEthPHYRGMIITX(Module): @@ -149,19 +149,13 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): ] # Reset + reset = Signal() if with_hw_init_reset: - reset = Signal() - counter_done = Signal() - counter = Signal(max=512) - counter_ce = Signal() - self.sync += If(counter_ce, counter.eq(counter + 1)) - self.comb += [ - counter_done.eq(counter == 256), - counter_ce.eq(~counter_done), - reset.eq(~counter_done | self._reset.storage) - ] + self.submodules.hw_reset = LiteEthPHYHWReset() + self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: - reset = self._reset.storage + self.comb += reset.eq(self._reset.storage) + self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset),