From 1f46aaeb55d5fe71def5ebf3abfd68311a7575b1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 15 Mar 2016 19:47:36 +0100 Subject: [PATCH] core/mac: remove frontend directory (too much directories) and some cleanup --- liteeth/core/mac/__init__.py | 2 +- .../core/mac/{core/__init__.py => core.py} | 2 +- liteeth/core/mac/{core => }/crc.py | 6 +---- liteeth/core/mac/frontend/__init__.py | 0 liteeth/core/mac/{core => }/gap.py | 5 ++++- liteeth/core/mac/{core => }/last_be.py | 0 liteeth/core/mac/{core => }/padding.py | 6 +++-- liteeth/core/mac/{core => }/preamble.py | 0 liteeth/core/mac/{frontend => }/sram.py | 22 ++++++++++--------- liteeth/core/mac/{frontend => }/wishbone.py | 2 +- 10 files changed, 24 insertions(+), 21 deletions(-) rename liteeth/core/mac/{core/__init__.py => core.py} (98%) rename liteeth/core/mac/{core => }/crc.py (97%) delete mode 100644 liteeth/core/mac/frontend/__init__.py rename liteeth/core/mac/{core => }/gap.py (93%) rename liteeth/core/mac/{core => }/last_be.py (100%) rename liteeth/core/mac/{core => }/padding.py (93%) rename liteeth/core/mac/{core => }/preamble.py (100%) rename liteeth/core/mac/{frontend => }/sram.py (94%) rename liteeth/core/mac/{frontend => }/wishbone.py (97%) diff --git a/liteeth/core/mac/__init__.py b/liteeth/core/mac/__init__.py index b6d203b..99fe92a 100644 --- a/liteeth/core/mac/__init__.py +++ b/liteeth/core/mac/__init__.py @@ -1,7 +1,7 @@ from liteeth.common import * from liteeth.core.mac.common import * from liteeth.core.mac.core import LiteEthMACCore -from liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface +from liteeth.core.mac.wishbone import LiteEthMACWishboneInterface class LiteEthMAC(Module, AutoCSR): diff --git a/liteeth/core/mac/core/__init__.py b/liteeth/core/mac/core.py similarity index 98% rename from liteeth/core/mac/core/__init__.py rename to liteeth/core/mac/core.py index 96a4d8e..561fcf6 100644 --- a/liteeth/core/mac/core/__init__.py +++ b/liteeth/core/mac/core.py @@ -1,5 +1,5 @@ from liteeth.common import * -from liteeth.core.mac.core import gap, preamble, crc, padding, last_be +from liteeth.core.mac import gap, preamble, crc, padding, last_be from liteeth.phy.model import LiteEthPHYModel diff --git a/liteeth/core/mac/core/crc.py b/liteeth/core/mac/crc.py similarity index 97% rename from liteeth/core/mac/core/crc.py rename to liteeth/core/mac/crc.py index 9a877af..43bd888 100644 --- a/liteeth/core/mac/core/crc.py +++ b/liteeth/core/mac/crc.py @@ -140,7 +140,6 @@ class LiteEthMACCRCInserter(Module): def __init__(self, crc_class, description): self.sink = sink = stream.Endpoint(description) self.source = source = stream.Endpoint(description) - self.busy = Signal() # # # @@ -160,7 +159,7 @@ class LiteEthMACCRCInserter(Module): fsm.act("COPY", crc.ce.eq(sink.stb & source.ack), crc.data.eq(sink.data), - sink.connect(source, leave_out=set(["eop"])), + sink.connect(source), source.eop.eq(0), If(sink.stb & sink.eop & source.ack, NextState("INSERT"), @@ -192,7 +191,6 @@ class LiteEthMACCRCInserter(Module): source.data.eq(crc.value), If(source.ack, NextState("IDLE")) ) - self.comb += self.busy.eq(~fsm.ongoing("IDLE")) class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter): @@ -221,7 +219,6 @@ class LiteEthMACCRCChecker(Module): def __init__(self, crc_class, description): self.sink = sink = stream.Endpoint(description) self.source = source = stream.Endpoint(description) - self.busy = Signal() # # # @@ -278,7 +275,6 @@ class LiteEthMACCRCChecker(Module): ) ) ) - self.comb += self.busy.eq(~fsm.ongoing("IDLE")) class LiteEthMACCRC32Checker(LiteEthMACCRCChecker): diff --git a/liteeth/core/mac/frontend/__init__.py b/liteeth/core/mac/frontend/__init__.py deleted file mode 100644 index e69de29..0000000 diff --git a/liteeth/core/mac/core/gap.py b/liteeth/core/mac/gap.py similarity index 93% rename from liteeth/core/mac/core/gap.py rename to liteeth/core/mac/gap.py index f36ead0..7a5ad92 100644 --- a/liteeth/core/mac/core/gap.py +++ b/liteeth/core/mac/gap.py @@ -1,5 +1,8 @@ +import math + from liteeth.common import * + class LiteEthMACGap(Module): def __init__(self, dw, ack_on_gap=False): self.sink = sink = stream.Endpoint(eth_phy_description(dw)) @@ -7,7 +10,7 @@ class LiteEthMACGap(Module): # # # - gap = ceil(eth_interpacket_gap/(dw//8)) + gap = math.ceil(eth_interpacket_gap/(dw//8)) counter = Signal(max=gap) counter_reset = Signal() counter_ce = Signal() diff --git a/liteeth/core/mac/core/last_be.py b/liteeth/core/mac/last_be.py similarity index 100% rename from liteeth/core/mac/core/last_be.py rename to liteeth/core/mac/last_be.py diff --git a/liteeth/core/mac/core/padding.py b/liteeth/core/mac/padding.py similarity index 93% rename from liteeth/core/mac/core/padding.py rename to liteeth/core/mac/padding.py index 47e04f0..ad02f7c 100644 --- a/liteeth/core/mac/core/padding.py +++ b/liteeth/core/mac/padding.py @@ -1,3 +1,5 @@ +import math + from liteeth.common import * @@ -8,7 +10,7 @@ class LiteEthMACPaddingInserter(Module): # # # - padding_limit = ceil(padding/(dw/8))-1 + padding_limit = math.ceil(padding/(dw/8))-1 counter = Signal(16, reset=1) counter_done = Signal() @@ -57,7 +59,7 @@ class LiteEthMACPaddingChecker(Module): # # # - # XXX see if we should drop the packet when + # TODO: see if we should drop the packet when # payload size < minimum ethernet payload size self.comb += sink.connect(source) diff --git a/liteeth/core/mac/core/preamble.py b/liteeth/core/mac/preamble.py similarity index 100% rename from liteeth/core/mac/core/preamble.py rename to liteeth/core/mac/preamble.py diff --git a/liteeth/core/mac/frontend/sram.py b/liteeth/core/mac/sram.py similarity index 94% rename from liteeth/core/mac/frontend/sram.py rename to liteeth/core/mac/sram.py index 5d75391..59fb535 100644 --- a/liteeth/core/mac/frontend/sram.py +++ b/liteeth/core/mac/sram.py @@ -40,11 +40,12 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): counter = Signal(lengthbits) counter_reset = Signal() counter_ce = Signal() - self.sync += If(counter_reset, - counter.eq(0) - ).Elif(counter_ce, - counter.eq(counter + increment) - ) + self.sync += \ + If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + increment) + ) # slot computation slot = Signal(slotbits) @@ -156,11 +157,12 @@ class LiteEthMACSRAMReader(Module, AutoCSR): counter = Signal(lengthbits) counter_reset = Signal() counter_ce = Signal() - self.sync += If(counter_reset, - counter.eq(0) - ).Elif(counter_ce, - counter.eq(counter + 4) - ) + self.sync += \ + If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + 4) + ) # fsm diff --git a/liteeth/core/mac/frontend/wishbone.py b/liteeth/core/mac/wishbone.py similarity index 97% rename from liteeth/core/mac/frontend/wishbone.py rename to liteeth/core/mac/wishbone.py index 2bf50b8..c006345 100644 --- a/liteeth/core/mac/frontend/wishbone.py +++ b/liteeth/core/mac/wishbone.py @@ -1,5 +1,5 @@ from liteeth.common import * -from liteeth.core.mac.frontend import sram +from liteeth.core.mac import sram from litex.soc.interconnect import wishbone from litex.gen.fhdl.simplify import FullMemoryWE