From 208bc095d9b353877695d7a1bac83efc0b1ce1f4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 11 Feb 2020 21:45:46 +0100 Subject: [PATCH] liteeth/gen: update --- liteeth/gen.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index 678075f..9c604e9 100644 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -210,13 +210,14 @@ class MACCore(PHYCore): PHYCore.__init__(self, phy, clk_freq) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") class _WishboneBridge(Module): def __init__(self, interface): self.wishbone = interface + self.wishbone.data_width = 32 bridge = _WishboneBridge(self.platform.request("wishbone")) self.submodules += bridge