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liteeth
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Fix all remaining indentation issues in python code 

I ran a script that shouldn't have missed any tab in the python source files.
This commit is contained in:
Felix Held 2018-01-13 13:23:18 +11:00
parent 2788294834
commit 20af2bf201
2 changed files with 22 additions and 22 deletions
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14
liteeth/phy/gmii.py
View File

@ -55,14 +55,14 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
# MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx # MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx
self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx")) self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
if isinstance(mii_mode, int) and (mii_mode == 0): if isinstance(mii_mode, int) and (mii_mode == 0):
self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk) self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
else: else:
# XXX Xilinx specific, replace BUFGMUX with a generic clock buffer? # XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
self.specials += Instance("BUFGMUX", self.specials += Instance("BUFGMUX",
i_I0=self.cd_eth_rx.clk, i_I0=self.cd_eth_rx.clk,
i_I1=clock_pads.tx, i_I1=clock_pads.tx,
i_S=mii_mode, i_S=mii_mode,
o_O=self.cd_eth_tx.clk) o_O=self.cd_eth_tx.clk)
reset = Signal() reset = Signal()
if with_hw_init_reset: if with_hw_init_reset:

30
setup.py
View File

@ -10,26 +10,26 @@ if sys.version_info[:3] < (3, 3):
setup( setup(
name="liteeth", name="liteeth",
version="0.1", version="0.1",
description="small footprint and configurable Ethernet core", description="small footprint and configurable Ethernet core",
long_description=open("README").read(), long_description=open("README").read(),
author="Florent Kermarrec", author="Florent Kermarrec",
author_email="florent@enjoy-digital.fr", author_email="florent@enjoy-digital.fr",
url="http://enjoy-digital.fr", url="http://enjoy-digital.fr",
download_url="https://github.com/enjoy-digital/liteeth", download_url="https://github.com/enjoy-digital/liteeth",
test_suite="test", test_suite="test",
license="BSD", license="BSD",
platforms=["Any"], platforms=["Any"],
keywords="HDL ASIC FPGA hardware design", keywords="HDL ASIC FPGA hardware design",
classifiers=[ classifiers=[
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
"Environment :: Console", "Environment :: Console",
"Development Status :: Alpha", "Development Status :: Alpha",
"Intended Audience :: Developers", "Intended Audience :: Developers",
"License :: OSI Approved :: BSD License", "License :: OSI Approved :: BSD License",
"Operating System :: OS Independent", "Operating System :: OS Independent",
"Programming Language :: Python", "Programming Language :: Python",
], ],
packages=find_packages(), packages=find_packages(),
include_package_data=True, include_package_data=True,