From 211cdc26f3359bb959a18f8d9fd34d29465e2b24 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 4 Apr 2024 17:26:54 +0200 Subject: [PATCH] core/ip: Add optional input buffer on LiteEthIPTX to improve timings. --- liteeth/core/ip.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py index 84e8e28..65639b9 100644 --- a/liteeth/core/ip.py +++ b/liteeth/core/ip.py @@ -94,13 +94,19 @@ class LiteEthIPV4Packetizer(Packetizer): class LiteEthIPTX(LiteXModule): - def __init__(self, mac_address, ip_address, arp_table, dw=8): + def __init__(self, mac_address, ip_address, arp_table, dw=8, with_buffer=False): self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw)) self.source = source = stream.Endpoint(eth_mac_description(dw)) self.target_unreachable = Signal() # # # + # Buffer. + if with_buffer: + self.buffer = buffer = stream.Buffer(eth_ipv4_user_description(dw)) + self.comb += sink.connect(buffer.sink) + sink = buffer.source + # Checksum. self.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True) self.comb += checksum.ce.eq(sink.valid)