From 263eb1244f4cce134ab9694b2ff58a897e4d2c96 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 13 Jun 2023 16:33:22 +0200
Subject: [PATCH] phy: Rename usp_1000basex to usp_gty_1000basex and update
 xcu1525.

---
 bench/xcu1525.py                                   | 14 ++++----------
 .../phy/{usp_1000basex.py => usp_gty_1000basex.py} |  8 ++++----
 2 files changed, 8 insertions(+), 14 deletions(-)
 rename liteeth/phy/{usp_1000basex.py => usp_gty_1000basex.py} (99%)

diff --git a/bench/xcu1525.py b/bench/xcu1525.py
index c7f2e36..2aa69bc 100755
--- a/bench/xcu1525.py
+++ b/bench/xcu1525.py
@@ -22,13 +22,12 @@ from litex.soc.interconnect.csr import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
 
-from liteeth.phy.usp_1000basex import USP_1000BASEX
+from liteeth.phy.usp_gty_1000basex import USP_GTY_1000BASEX
 
 # IOs ----------------------------------------------------------------------------------------------
 
 _qsfp_io = [
     # QSFP0
-    ("qsfp_fs", 0, Pins("AT20 AU22"), IOStandard("LVCMOS12")),
     ("qsfp", 0,
         Subsignal("txp", Pins("N9")),
         Subsignal("txn", Pins("N8")),
@@ -41,8 +40,8 @@ _qsfp_io = [
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
-        self.cd_sys     = ClockDomain()
-        self.cd_eth     = ClockDomain()
+        self.cd_sys = ClockDomain()
+        self.cd_eth = ClockDomain()
 
         # # #
 
@@ -72,10 +71,9 @@ class BenchSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # Etherbone --------------------------------------------------------------------------------
-        self.ethphy = USP_1000BASEX(self.crg.cd_eth.clk,
+        self.ethphy = USP_GTY_1000BASEX(self.crg.cd_eth.clk,
             data_pads    = self.platform.request("qsfp", 0),
             sys_clk_freq = self.clk_freq)
-        self.comb += self.platform.request("qsfp_fs").eq(0b01)
         self.add_etherbone(phy=self.ethphy, buffer_depth=255)
 
         # SRAM -------------------------------------------------------------------------------------
@@ -89,7 +87,6 @@ class BenchSoC(SoCCore):
         )
 
         # Litescope --------------------------------------------------------------------------------
-
         from litescope import LiteScopeAnalyzer
         analyzer_signals = self.ethphy.debug
         self.analyzer = LiteScopeAnalyzer(analyzer_signals,
@@ -99,9 +96,6 @@ class BenchSoC(SoCCore):
         )
 
 
-
-
-
 # Main ---------------------------------------------------------------------------------------------
 
 def main():
diff --git a/liteeth/phy/usp_1000basex.py b/liteeth/phy/usp_gty_1000basex.py
similarity index 99%
rename from liteeth/phy/usp_1000basex.py
rename to liteeth/phy/usp_gty_1000basex.py
index 79a8a55..0418b70 100644
--- a/liteeth/phy/usp_1000basex.py
+++ b/liteeth/phy/usp_gty_1000basex.py
@@ -1,7 +1,7 @@
 #
 # This file is part of LiteEth.
 #
-# Copyright (c) 2019-2021 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2019-2023 Florent Kermarrec <florent@enjoy-digital.fr>
 # Copyright (c) 2018 Sebastien Bourdeauducq <sb@m-labs.hk>
 # SPDX-License-Identifier: BSD-2-Clause
 
@@ -16,9 +16,9 @@ from litex.gen import *
 from liteeth.common import *
 from liteeth.phy.pcs_1000basex import *
 
-# USP_1000BASEX PHY ---------------------------------------------------------------------------------
+# USP_GTY_1000BASEX PHY ----------------------------------------------------------------------------
 
-class USP_1000BASEX(LiteXModule):
+class USP_GTY_1000BASEX(LiteXModule):
     # Configured for 200MHz transceiver reference clock.
     dw          = 8
     tx_clk_freq = 125e6
@@ -956,7 +956,7 @@ class USP_1000BASEX(LiteXModule):
             gearbox.rx_data_half.eq(rx_data),
 
             gearbox.tx_data.eq(pcs.tbi_tx),
-              pcs.tbi_rx.eq(gearbox.rx_data)
+            pcs.tbi_rx.eq(gearbox.rx_data)
         ]
 
         self.debug = [