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liteeth_gen: Finish adding Etherbone support.

This commit is contained in:
Florent Kermarrec 2023-06-22 21:36:38 +02:00
parent 52e94c02b5
commit 2681a4f5d1
1 changed files with 11 additions and 5 deletions
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16
liteeth/gen.py
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@ -344,16 +344,22 @@ class UDPCore(PHYCore):
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
# /!\ WIP /!\ etherbone = core_config.get("etherbone", False)
with_etherbone = False etherbone_port = core_config.get("etherbone_port", 1234)
if with_etherbone: etherbone_buffer_depth = core_config.get("etherbone_buffer_depth", 16)
if etherbone:
assert (data_width == 32) assert (data_width == 32)
self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, buffer_depth=16, cd="sys") self.submodules.etherbone = LiteEthEtherbone(
udp = self.core.udp,
udp_port = etherbone_port,
buffer_depth = etherbone_buffer_depth,
cd = "sys"
)
axil_bus = axi.AXILiteInterface(address_width=32, data_width=32) axil_bus = axi.AXILiteInterface(address_width=32, data_width=32)
platform.add_extension(axil_bus.get_ios("mmap")) platform.add_extension(axil_bus.get_ios("mmap"))
self.submodules += axi.Wishbone2AXILite(self.etherbone.wishbone.bus, axil_bus) self.submodules += axi.Wishbone2AXILite(self.etherbone.wishbone.bus, axil_bus)
self.comb += axil_bus.connect_to_pads(platform.request("mmap"), mode="master") self.comb += axil_bus.connect_to_pads(platform.request("mmap"), mode="master")
# /!\ WIP /!\
# UDP Ports -------------------------------------------------------------------------------- # UDP Ports --------------------------------------------------------------------------------
for name, port in core_config["udp_ports"].items(): for name, port in core_config["udp_ports"].items():