From 27882948345fca48ee9e833c7b46c1a23c9669cd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 31 Dec 2017 07:12:55 +0100 Subject: [PATCH] core/mac/sram: add csr for fifo level of sram reader (for the linux driver) --- liteeth/core/mac/sram.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/liteeth/core/mac/sram.py b/liteeth/core/mac/sram.py index 47a8d75..fc9fd1f 100644 --- a/liteeth/core/mac/sram.py +++ b/liteeth/core/mac/sram.py @@ -149,6 +149,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR): self._start = CSR() self._ready = CSRStatus() + self._level = CSRStatus(log2_int(nslots) + 1) self._slot = CSRStorage(slotbits) self._length = CSRStorage(lengthbits) @@ -165,7 +166,8 @@ class LiteEthMACSRAMReader(Module, AutoCSR): fifo.sink.valid.eq(self._start.re), fifo.sink.slot.eq(self._slot.storage), fifo.sink.length.eq(self._length.storage), - self._ready.status.eq(fifo.sink.ready) + self._ready.status.eq(fifo.sink.ready), + self._level.status.eq(fifo.level) ] # length computation