From 7ac3fe681a414594ee29c94de1ac98cdb61242b5 Mon Sep 17 00:00:00 2001
From: Anton Blanchard <anton@ozlabs.org>
Date: Thu, 5 Aug 2021 16:05:12 +1000
Subject: [PATCH] liteeth/gen: Allow configuration of nrxslots and ntxslots

We might want to increase nrxslots and ntxslots to improve
performance, so allow it to be overriden via the yaml config.
---
 liteeth/gen.py | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/liteeth/gen.py b/liteeth/gen.py
index 2b04897..9b62b75 100755
--- a/liteeth/gen.py
+++ b/liteeth/gen.py
@@ -213,14 +213,20 @@ class MACCore(PHYCore):
         # PHY --------------------------------------------------------------------------------------
         PHYCore.__init__(self, platform, core_config)
 
+        nrxslots = core_config.get("nrxslots", 2)
+        ntxslots = core_config.get("ntxslots", 2)
+        mac_memsize = (nrxslots + ntxslots) * buffer_depth
+
         # MAC --------------------------------------------------------------------------------------
         self.submodules.ethmac = LiteEthMAC(
             phy        = self.ethphy,
             dw         = 32,
             interface  = "wishbone",
-            endianness = core_config["endianness"])
+            endianness = core_config["endianness"],
+            nrxslots   = nrxslots,
+            ntxslots   = ntxslots)
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+        self.add_memory_region("ethmac", self.mem_map["ethmac"], mac_memsize, type="io")
         self.add_csr("ethmac")
 
         # Wishbone Interface -----------------------------------------------------------------------