diff --git a/liteeth/mac/core.py b/liteeth/mac/core.py
index fd782f4..dd846ed 100644
--- a/liteeth/mac/core.py
+++ b/liteeth/mac/core.py
@@ -10,7 +10,6 @@
 
 from liteeth.common import *
 from liteeth.mac import gap, preamble, crc, padding, last_be
-from liteeth.phy.model import LiteEthPHYModel
 
 from migen.genlib.cdc import PulseSynchronizer
 
@@ -46,8 +45,12 @@ class LiteEthMACCore(Module, AutoCSR):
             cd_tx       = "eth_tx"
             cd_rx       = "eth_rx"
             datapath_dw = phy_dw
-        if isinstance(phy, LiteEthPHYModel):
-            with_preamble_crc = False # Disable Preamble/CRC with PHY Model for direct connection to the Ethernet tap.
+
+        # If the PHY specifies preamble, CRC, or padding behavior, use it.
+        if hasattr(phy, "with_preamble_crc"):
+            with_preamble_crc = phy.with_preamble_crc
+        if hasattr(phy, "with_padding"):
+            with_padding = phy.with_padding
 
         # CSRs.
         if with_preamble_crc:
diff --git a/liteeth/phy/model.py b/liteeth/phy/model.py
index 6aa3bd3..7bb0dba 100644
--- a/liteeth/phy/model.py
+++ b/liteeth/phy/model.py
@@ -34,7 +34,8 @@ class LiteEthPHYModelCRG(LiteXModule):
 # LiteEth PHY Model --------------------------------------------------------------------------------
 
 class LiteEthPHYModel(LiteXModule):
-    dw = 8
+    dw                = 8
+    with_preamble_crc = False # Disable Preamble/CRC with for direct connection to the Ethernet tap.
     def __init__(self, pads):
         self.crg    = LiteEthPHYModelCRG()
         self.sink   = sink   = stream.Endpoint(eth_phy_description(8))