liteeth/mac/core: Allow PHY to enforce with_preamble_crc/with_padding parameters.
Avoid exposing these parameters up to add_ethernet since appropriate behaviour is generally directly related to the type of PHY (ex LiteEthPHYModel or custom/specialized PHY).
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@ -10,7 +10,6 @@
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from liteeth.common import *
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from liteeth.common import *
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from liteeth.mac import gap, preamble, crc, padding, last_be
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from liteeth.mac import gap, preamble, crc, padding, last_be
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from liteeth.phy.model import LiteEthPHYModel
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from migen.genlib.cdc import PulseSynchronizer
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from migen.genlib.cdc import PulseSynchronizer
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@ -46,8 +45,12 @@ class LiteEthMACCore(Module, AutoCSR):
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cd_tx = "eth_tx"
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cd_tx = "eth_tx"
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cd_rx = "eth_rx"
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cd_rx = "eth_rx"
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datapath_dw = phy_dw
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datapath_dw = phy_dw
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if isinstance(phy, LiteEthPHYModel):
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with_preamble_crc = False # Disable Preamble/CRC with PHY Model for direct connection to the Ethernet tap.
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# If the PHY specifies preamble, CRC, or padding behavior, use it.
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if hasattr(phy, "with_preamble_crc"):
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with_preamble_crc = phy.with_preamble_crc
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if hasattr(phy, "with_padding"):
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with_padding = phy.with_padding
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# CSRs.
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# CSRs.
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if with_preamble_crc:
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if with_preamble_crc:
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@ -34,7 +34,8 @@ class LiteEthPHYModelCRG(LiteXModule):
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# LiteEth PHY Model --------------------------------------------------------------------------------
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# LiteEth PHY Model --------------------------------------------------------------------------------
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class LiteEthPHYModel(LiteXModule):
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class LiteEthPHYModel(LiteXModule):
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dw = 8
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dw = 8
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with_preamble_crc = False # Disable Preamble/CRC with for direct connection to the Ethernet tap.
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def __init__(self, pads):
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def __init__(self, pads):
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self.crg = LiteEthPHYModelCRG()
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self.crg = LiteEthPHYModelCRG()
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self.sink = sink = stream.Endpoint(eth_phy_description(8))
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self.sink = sink = stream.Endpoint(eth_phy_description(8))
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