From 2b6dfa6a7e63297070b3aa5ed7fcc85dad375627 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 24 Oct 2015 13:19:52 +0200 Subject: [PATCH] cleanup (remove use of FlipFlop) --- liteeth/common.py | 9 ------- liteeth/core/arp.py | 50 ++++++++++++++++++++++------------- liteeth/frontend/etherbone.py | 22 ++++++++------- liteeth/frontend/tty.py | 15 ++++++----- liteeth/phy/rmii.py | 14 ++++++---- 5 files changed, 61 insertions(+), 49 deletions(-) diff --git a/liteeth/common.py b/liteeth/common.py index bbed30b..e89d0e1 100644 --- a/liteeth/common.py +++ b/liteeth/common.py @@ -21,15 +21,6 @@ def reverse_bytes(signal): return Cat(*r) -@ResetInserter() -@CEInserter() -class FlipFlop(Module): - def __init__(self, *args, **kwargs): - self.d = Signal(*args, **kwargs) - self.q = Signal(*args, **kwargs) - self.sync += self.q.eq(self.d) - - @ResetInserter() @CEInserter() class Counter(Module): diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py index b28c858..1f136f5 100644 --- a/liteeth/core/arp.py +++ b/liteeth/core/arp.py @@ -150,16 +150,30 @@ class LiteEthARPTable(Module): # # # + request_pending = Signal() + request_pending_clr = Signal() + request_pending_set = Signal() + self.sync += \ + If(request_pending_clr, + request_pending.eq(0) + ).Elif(request_pending_set, + request_pending.eq(1) + ) + + request_ip_address = Signal(32) + request_ip_address_reset = Signal() + request_ip_address_update = Signal() + self.sync += \ + If(request_ip_address_reset, + request_ip_address.eq(0) + ).Elif(request_ip_address_update, + request_ip_address.eq(request.ip_address) + ) + request_timer = WaitTimer(clk_freq//10) request_counter = Counter(max=max_requests) - request_pending = FlipFlop() - request_ip_address = FlipFlop(32) - self.submodules += request_timer, request_counter, request_pending, request_ip_address - self.comb += [ - request_timer.wait.eq(request_pending.q & ~request_counter.ce), - request_pending.d.eq(1), - request_ip_address.d.eq(request.ip_address) - ] + self.submodules += request_timer, request_counter + self.comb += request_timer.wait.eq(request_pending & ~request_counter.ce) # Note: Store only 1 IP/MAC couple, can be improved with a real # table in the future to improve performance when packets are @@ -177,11 +191,11 @@ class LiteEthARPTable(Module): # is lost. This is compensated by the protocol (retries) If(sink.stb & sink.request, NextState("SEND_REPLY") - ).Elif(sink.stb & sink.reply & request_pending.q, + ).Elif(sink.stb & sink.reply & request_pending, NextState("UPDATE_TABLE"), ).Elif(request_counter.value == max_requests-1, NextState("PRESENT_RESPONSE") - ).Elif(request.stb | (request_pending.q & request_timer.done), + ).Elif(request.stb | (request_pending & request_timer.done), NextState("CHECK_TABLE") ) ) @@ -195,7 +209,7 @@ class LiteEthARPTable(Module): ) ) fsm.act("UPDATE_TABLE", - request_pending.reset.eq(1), + request_pending_clr.eq(1), update.eq(1), NextState("CHECK_TABLE") ) @@ -213,29 +227,29 @@ class LiteEthARPTable(Module): found = Signal() fsm.act("CHECK_TABLE", If(cached_valid, - If(request_ip_address.q == cached_ip_address, - request_ip_address.reset.eq(1), + If(request_ip_address == cached_ip_address, + request_ip_address_reset.eq(1), NextState("PRESENT_RESPONSE"), ).Elif(request.ip_address == cached_ip_address, request.ack.eq(request.stb), NextState("PRESENT_RESPONSE"), ).Else( - request_ip_address.ce.eq(request.stb), + request_ip_address_update.eq(request.stb), NextState("SEND_REQUEST") ) ).Else( - request_ip_address.ce.eq(request.stb), + request_ip_address_update.eq(request.stb), NextState("SEND_REQUEST") ) ) fsm.act("SEND_REQUEST", source.stb.eq(1), source.request.eq(1), - source.ip_address.eq(request_ip_address.q), + source.ip_address.eq(request_ip_address), If(source.ack, request_counter.reset.eq(request.stb), request_counter.ce.eq(1), - request_pending.ce.eq(1), + request_pending_set.eq(1), request.ack.eq(1), NextState("IDLE") ) @@ -244,7 +258,7 @@ class LiteEthARPTable(Module): If(request_counter == max_requests-1, response.failed.eq(1), request_counter.reset.eq(1), - request_pending.reset.eq(1) + request_pending_clr.eq(1) ), response.mac_address.eq(cached_mac_address) ] diff --git a/liteeth/frontend/etherbone.py b/liteeth/frontend/etherbone.py index a9116a7..711a10f 100644 --- a/liteeth/frontend/etherbone.py +++ b/liteeth/frontend/etherbone.py @@ -194,8 +194,9 @@ class LiteEthEtherboneRecordReceiver(Module): self.submodules += fifo self.comb += Record.connect(sink, fifo.sink) - self.submodules.base_addr = base_addr = FlipFlop(32) - self.comb += base_addr.d.eq(fifo.source.data) + base_addr = Signal(32) + base_addr_update = Signal() + self.sync += If(base_addr_update, base_addr.eq(fifo.source.data)) self.submodules.counter = counter = Counter(max=512) @@ -204,7 +205,7 @@ class LiteEthEtherboneRecordReceiver(Module): fifo.source.ack.eq(1), counter.reset.eq(1), If(fifo.source.stb & fifo.source.sop, - base_addr.ce.eq(1), + base_addr_update.eq(1), If(fifo.source.wcount, NextState("RECEIVE_WRITES") ).Elif(fifo.source.rcount, @@ -218,7 +219,7 @@ class LiteEthEtherboneRecordReceiver(Module): source.eop.eq(counter.value == fifo.source.wcount-1), source.count.eq(fifo.source.wcount), source.be.eq(fifo.source.byte_enable), - source.addr.eq(base_addr.q[2:] + counter.value), + source.addr.eq(base_addr[2:] + counter.value), source.we.eq(1), source.data.eq(fifo.source.data), fifo.source.ack.eq(source.ack), @@ -236,7 +237,7 @@ class LiteEthEtherboneRecordReceiver(Module): fsm.act("RECEIVE_BASE_RET_ADDR", counter.reset.eq(1), If(fifo.source.stb & fifo.source.sop, - base_addr.ce.eq(1), + base_addr_update.eq(1), NextState("RECEIVE_READS") ) ) @@ -245,7 +246,7 @@ class LiteEthEtherboneRecordReceiver(Module): source.sop.eq(counter.value == 0), source.eop.eq(counter.value == fifo.source.rcount-1), source.count.eq(fifo.source.rcount), - source.base_addr.eq(base_addr.q), + source.base_addr.eq(base_addr), source.addr.eq(fifo.source.data[2:]), fifo.source.ack.eq(source.ack), If(source.stb & source.ack, @@ -360,8 +361,9 @@ class LiteEthEtherboneWishboneMaster(Module): # # # - self.submodules.data = data = FlipFlop(32) - self.comb += data.d.eq(bus.dat_r) + data = Signal(32) + data_update = Signal() + self.sync += If(data_update, data.eq(bus.dat_r)) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", @@ -395,7 +397,7 @@ class LiteEthEtherboneWishboneMaster(Module): bus.stb.eq(sink.stb), bus.cyc.eq(1), If(bus.stb & bus.ack, - data.ce.eq(1), + data_update.eq(1), NextState("SEND_DATA") ) ) @@ -408,7 +410,7 @@ class LiteEthEtherboneWishboneMaster(Module): source.count.eq(sink.count), source.be.eq(sink.be), source.we.eq(1), - source.data.eq(data.q), + source.data.eq(data), If(source.stb & source.ack, sink.ack.eq(1), If(source.eop, diff --git a/liteeth/frontend/tty.py b/liteeth/frontend/tty.py index ad2d07b..b98c8c6 100644 --- a/liteeth/frontend/tty.py +++ b/liteeth/frontend/tty.py @@ -21,15 +21,16 @@ class LiteEthTTYTX(Module): self.submodules.fifo = fifo = SyncFIFO([("data", 8)], fifo_depth) self.comb += Record.connect(sink, fifo.sink) - self.submodules.level = level = FlipFlop(max=fifo_depth) - self.comb += level.d.eq(fifo.fifo.level) + level = Signal(max=fifo_depth) + level_update = Signal() + self.sync += If(level_update, level.eq(fifo.fifo.level)) self.submodules.counter = counter = Counter(max=fifo_depth) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", If(fifo.source.stb, - level.ce.eq(1), + level_update.eq(1), counter.reset.eq(1), NextState("SEND") ) @@ -37,18 +38,18 @@ class LiteEthTTYTX(Module): fsm.act("SEND", source.stb.eq(fifo.source.stb), source.sop.eq(counter.value == 0), - If(level.q == 0, + If(level == 0, source.eop.eq(1), ).Else( - source.eop.eq(counter.value == (level.q-1)), + source.eop.eq(counter.value == (level-1)), ), source.src_port.eq(udp_port), source.dst_port.eq(udp_port), source.ip_address.eq(ip_address), - If(level.q == 0, + If(level == 0, source.length.eq(1), ).Else( - source.length.eq(level.q), + source.length.eq(level), ), source.data.eq(fifo.source.data), fifo.source.ack.eq(source.ack), diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index 64c8383..1cee6b4 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -37,8 +37,10 @@ class LiteEthPHYRMIIRX(Module): # # # - sop = FlipFlop(reset=1) - self.submodules += sop + sop = Signal(reset=1) + sop_set = Signal() + sop_clr = Signal() + self.sync += If(sop_set, sop.eq(1)).Elif(sop_clr, sop.eq(0)) converter = Converter(converter_description(2), converter_description(8)) @@ -50,10 +52,12 @@ class LiteEthPHYRMIIRX(Module): converter.sink.stb.eq(1), converter.sink.data.eq(pads.rx_data) ] + self.sync += [ + sop_set.eq(~pads.dv), + sop_clr.eq(pads.dv) + ] self.comb += [ - sop.reset.eq(~pads.dv), - sop.ce.eq(pads.dv), - converter.sink.sop.eq(sop.q), + converter.sink.sop.eq(sop), converter.sink.eop.eq(~pads.dv) ] self.comb += Record.connect(converter.source, source)