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examples: Improve identation/presentation.

This commit is contained in:
Florent Kermarrec 2024-03-18 13:43:11 +01:00
parent e3a5d6fc19
commit 2c67d13456
6 changed files with 67 additions and 58 deletions
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16
examples/axi-lite-mii.yml
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@ -6,14 +6,16 @@
# SPDX-License-Identifier: BSD-2-Clause
# PHY ----------------------------------------------------------------------
phy: LiteEthPHYMII
vendor: xilinx
toolchain: vivado
# Core ---------------------------------------------------------------------
clk_freq: 100e6
core: axi-lite
endianness: big
phy : LiteEthPHYMII
vendor : xilinx
toolchain : vivado
# Core ---------------------------------------------------------------------
clk_freq : 100e6
core : axi-lite
endianness : big
# SoC ---------------------------------------------------------------------
soc:
mem_map:
ethmac: 0x50000000

8
examples/udp_a7_gtp_sgmii.yml
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@ -4,14 +4,14 @@
# Copyright (c) 2020-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
# PHY ----------------------------------------------------------------------
# PHY --------------------------------------------------------------------------
phy : A7_1000BASEX
phy_tx_polarity : 0
phy_rx_polarity : 0
vendor : xilinx
toolchain : vivado
# Core ---------------------------------------------------------------------
# Core -------------------------------------------------------------------------
refclk_freq : 156.25e6
clk_freq : 25e6
core : udp
@ -19,8 +19,8 @@ data_width : 32
dhcp : True
# UDP Ports --------------------------------------------------------------------
udp_ports: {
"udp0": {
udp_ports : {
"udp0" : {
"data_width" : 32,
"tx_fifo_depth" : 1024,
"rx_fifo_depth" : 1024,

53
examples/udp_raw_ecp5rgmii.yml
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@ -1,24 +1,29 @@
--- # PHY ----------------------------------------------------------------------
#
# This file is part of LiteEth.
#
# Copyright (c) 2023 LumiGuide Fietsdetectie B.V. <goemansrowan@gmail.com>
# License: BSD
# SPDX-License-Identifier: BSD-2-Clause
# PHY --------------------------------------------------------------------------
phy : LiteEthECP5PHYRGMII
phy_tx_delay : 0e-9
phy_rx_delay : 2e-9
device : LFE5U-25F-6BG256C
vendor : lattice
toolchain : trellis
phy: LiteEthECP5PHYRGMII
phy_tx_delay: 0e-9
phy_rx_delay: 2e-9
device: LFE5U-25F-6BG256C
vendor: lattice
toolchain: trellis
# Core -------------------------------------------------------------------------
clk_freq: 125e6
core: udp
clk_freq : 125e6
core : udp
mac_address: 0x10e2d5000000
ip_address: 172.30.0.1
mac_address : 0x10e2d5000000
ip_address : 172.30.0.1
tx_cdc_depth : 16
tx_cdc_buffered : True
rx_cdc_depth : 16
rx_cdc_buffered : True
tx_cdc_depth: 16
tx_cdc_buffered: True
rx_cdc_depth: 16
rx_cdc_buffered: True
# UDP Ports --------------------------------------------------------------------
# mode `raw` vs `streamer` mode:
# The streamer mode is a convenience wrapper around a `raw` UDP port. A raw UDP
@ -32,13 +37,13 @@ rx_cdc_buffered: True
# control of transmitted UDP packet sizes.
udp_ports:
raw:
data_width: 32
mode: raw
data_width : 32
mode : raw
streamer1:
data_width: 32
port: 1337
mode: streamer
data_width : 32
port : 1337
mode : streamer
streamer2:
data_width: 32
port: 6077
mode: streamer
data_width : 32
port : 6077
mode : streamer

22
examples/udp_s7phyrgmii.yml
View File

@ -5,27 +5,27 @@
# SPDX-License-Identifier: BSD-2-Clause
# PHY --------------------------------------------------------------------------
phy: LiteEthS7PHYRGMII
vendor: xilinx
toolchain: vivado
phy : LiteEthS7PHYRGMII
vendor : xilinx
toolchain : vivado
# Core -------------------------------------------------------------------------
clk_freq: 125e6
core: udp
mac_address: 0x10e2d5000000
ip_address: 192.168.1.50
data_width: 8
clk_freq : 125e6
core : udp
mac_address : 0x10e2d5000000
ip_address : 192.168.1.50
data_width : 8
# UDP Ports --------------------------------------------------------------------
udp_ports: {
"udp0": {
udp_ports : {
"udp0" : {
"udp_port" : 2000, # Static Params.
"ip_address" : "192.168.1.100", # Static Params.
"data_width" : 32,
"tx_fifo_depth" : 64,
"rx_fifo_depth" : 64,
},
"udp1": {
"udp1" : {
#"udp_port" : , # Dynamic Params.
#"ip_address" : , # Dynamic Params.
"data_width" : 32,

8
examples/udp_usp_gth_sgmii.yml
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@ -4,12 +4,12 @@
# Copyright (c) 2020-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
# PHY ----------------------------------------------------------------------
# PHY --------------------------------------------------------------------------
phy : USP_GTH_1000BASEX
vendor : xilinx
toolchain : vivado
# Core ---------------------------------------------------------------------
# Core -------------------------------------------------------------------------
refclk_freq : 156.25e6
clk_freq : 25e6
core : udp
@ -17,8 +17,8 @@ data_width : 32
dhcp : True
# UDP Ports --------------------------------------------------------------------
udp_ports: {
"udp0": {
udp_ports : {
"udp0" : {
"data_width" : 32,
"tx_fifo_depth" : 1024,
"rx_fifo_depth" : 1024,

18
examples/wishbone_mii.yml
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@ -4,15 +4,17 @@
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
# PHY ----------------------------------------------------------------------
phy: LiteEthPHYMII
vendor: xilinx
toolchain: vivado
# Core ---------------------------------------------------------------------
clk_freq: 100e6
core: wishbone
endianness: big
# PHY --------------------------------------------------------------------------
phy : LiteEthPHYMII
vendor : xilinx
toolchain : vivado
# Core -------------------------------------------------------------------------
clk_freq : 100e6
core : wishbone
endianness : big
# SoC --------------------------------------------------------------------------
soc:
mem_map:
ethmac: 0x50000000