diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py index 5497e2e..d5dad1a 100644 --- a/liteeth/core/arp.py +++ b/liteeth/core/arp.py @@ -10,9 +10,9 @@ from litex.soc.interconnect.packet import Depacketizer, Packetizer # ARP Layouts -------------------------------------------------------------------------------------- _arp_table_layout = [ - ("reply", 1), - ("request", 1), - ("ip_address", 32), + ("reply", 1), + ("request", 1), + ("ip_address", 32), ("mac_address", 48) ] @@ -28,27 +28,19 @@ class LiteEthARPPacketizer(Packetizer): class LiteEthARPTX(Module): def __init__(self, mac_address, ip_address, dw=8): - self.sink = sink = stream.Endpoint(_arp_table_layout) + self.sink = sink = stream.Endpoint(_arp_table_layout) self.source = source = stream.Endpoint(eth_mac_description(dw)) # # # - self.submodules.packetizer = packetizer = LiteEthARPPacketizer(dw) - counter = Signal(max=max(arp_header.length, eth_min_len), reset_less=True) - counter_reset = Signal() - counter_ce = Signal() - self.sync += \ - If(counter_reset, - counter.eq(0) - ).Elif(counter_ce, - counter.eq(counter + 1) - ) + + self.submodules.packetizer = packetizer = LiteEthARPPacketizer(dw) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", sink.ready.eq(1), - counter_reset.eq(1), + NextValue(counter, 0), If(sink.valid, sink.ready.eq(0), NextState("SEND") @@ -79,7 +71,7 @@ class LiteEthARPTX(Module): source.sender_mac.eq(mac_address), source.ethernet_type.eq(ethernet_type_arp), If(source.valid & source.ready, - counter_ce.eq(1), + NextValue(counter, counter + 1), If(source.last, sink.ready.eq(1), NextState("IDLE") @@ -99,10 +91,10 @@ class LiteEthARPDepacketizer(Depacketizer): class LiteEthARPRX(Module): def __init__(self, mac_address, ip_address, dw=8): - self.sink = sink = stream.Endpoint(eth_mac_description(dw)) + self.sink = sink = stream.Endpoint(eth_mac_description(dw)) self.source = source = stream.Endpoint(_arp_table_layout) - # # # + # # #s self.submodules.depacketizer = depacketizer = LiteEthARPDepacketizer(dw) self.comb += sink.connect(depacketizer.sink) @@ -154,16 +146,16 @@ class LiteEthARPRX(Module): class LiteEthARPTable(Module): def __init__(self, clk_freq, max_requests=8): - self.sink = sink = stream.Endpoint(_arp_table_layout) # from arp_rx - self.source = source = stream.Endpoint(_arp_table_layout) # to arp_tx + self.sink = sink = stream.Endpoint(_arp_table_layout) # from arp_rx + self.source = source = stream.Endpoint(_arp_table_layout) # to arp_tx # Request/Response interface - self.request = request = stream.Endpoint(arp_table_request_layout) + self.request = request = stream.Endpoint(arp_table_request_layout) self.response = response = stream.Endpoint(arp_table_response_layout) # # # - request_pending = Signal() + request_pending = Signal() request_pending_clr = Signal() request_pending_set = Signal() self.sync += \ @@ -173,8 +165,8 @@ class LiteEthARPTable(Module): request_pending.eq(1) ) - request_ip_address = Signal(32, reset_less=True) - request_ip_address_reset = Signal() + request_ip_address = Signal(32, reset_less=True) + request_ip_address_reset = Signal() request_ip_address_update = Signal() self.sync += \ If(request_ip_address_reset, @@ -185,9 +177,9 @@ class LiteEthARPTable(Module): request_timer = WaitTimer(clk_freq//10) self.submodules += request_timer - request_counter = Signal(max=max_requests) + request_counter = Signal(max=max_requests) request_counter_reset = Signal() - request_counter_ce = Signal() + request_counter_ce = Signal() self.sync += \ If(request_counter_reset, request_counter.eq(0) @@ -200,10 +192,10 @@ class LiteEthARPTable(Module): # table in the future to improve performance when packets are # targeting multiple destinations. update = Signal() - cached_valid = Signal() - cached_ip_address = Signal(32, reset_less=True) + cached_valid = Signal() + cached_ip_address = Signal(32, reset_less=True) cached_mac_address = Signal(48, reset_less=True) - cached_timer = WaitTimer(clk_freq*10) + cached_timer = WaitTimer(clk_freq*10) self.submodules += cached_timer self.submodules.fsm = fsm = FSM(reset_state="IDLE") @@ -293,8 +285,8 @@ class LiteEthARPTable(Module): class LiteEthARP(Module): def __init__(self, mac, mac_address, ip_address, clk_freq, dw=8): - self.submodules.tx = tx = LiteEthARPTX(mac_address, ip_address, dw) - self.submodules.rx = rx = LiteEthARPRX(mac_address, ip_address, dw) + self.submodules.tx = tx = LiteEthARPTX(mac_address, ip_address, dw) + self.submodules.rx = rx = LiteEthARPRX(mac_address, ip_address, dw) self.submodules.table = table = LiteEthARPTable(clk_freq) self.comb += [ rx.source.connect(table.sink), diff --git a/liteeth/core/icmp.py b/liteeth/core/icmp.py index d85150a..470524d 100644 --- a/liteeth/core/icmp.py +++ b/liteeth/core/icmp.py @@ -17,7 +17,7 @@ class LiteEthICMPPacketizer(Packetizer): class LiteEthICMPTX(Module): def __init__(self, ip_address, dw=8): - self.sink = sink = stream.Endpoint(eth_icmp_user_description(dw)) + self.sink = sink = stream.Endpoint(eth_icmp_user_description(dw)) self.source = source = stream.Endpoint(eth_ipv4_user_description(dw)) # # # @@ -64,7 +64,7 @@ class LiteEthICMPDepacketizer(Depacketizer): class LiteEthICMPRX(Module): def __init__(self, ip_address, dw=8): - self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw)) + self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw)) self.source = source = stream.Endpoint(eth_icmp_user_description(dw)) # # # @@ -123,7 +123,7 @@ class LiteEthICMPRX(Module): class LiteEthICMPEcho(Module): def __init__(self, dw=8): - self.sink = sink = stream.Endpoint(eth_icmp_user_description(dw)) + self.sink = sink = stream.Endpoint(eth_icmp_user_description(dw)) self.source = source = stream.Endpoint(eth_icmp_user_description(dw)) # # # @@ -141,8 +141,8 @@ class LiteEthICMPEcho(Module): class LiteEthICMP(Module): def __init__(self, ip, ip_address, dw=8): - self.submodules.tx = tx = LiteEthICMPTX(ip_address, dw) - self.submodules.rx = rx = LiteEthICMPRX(ip_address, dw) + self.submodules.tx = tx = LiteEthICMPTX(ip_address, dw) + self.submodules.rx = rx = LiteEthICMPRX(ip_address, dw) self.submodules.echo = echo = LiteEthICMPEcho(dw) self.comb += [ rx.source.connect(echo.sink), diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py index 8bb4c64..0044b40 100644 --- a/liteeth/core/ip.py +++ b/liteeth/core/ip.py @@ -10,15 +10,15 @@ from litex.soc.interconnect.packet import Depacketizer, Packetizer class LiteEthIPV4MasterPort: def __init__(self, dw): - self.dw = dw + self.dw = dw self.source = stream.Endpoint(eth_ipv4_user_description(dw)) - self.sink = stream.Endpoint(eth_ipv4_user_description(dw)) + self.sink = stream.Endpoint(eth_ipv4_user_description(dw)) class LiteEthIPV4SlavePort: def __init__(self, dw): - self.dw = dw - self.sink = stream.Endpoint(eth_ipv4_user_description(dw)) + self.dw = dw + self.sink = stream.Endpoint(eth_ipv4_user_description(dw)) self.source = stream.Endpoint(eth_ipv4_user_description(dw)) @@ -45,8 +45,8 @@ class LiteEthIPV4Crossbar(LiteEthCrossbar): class LiteEthIPV4Checksum(Module): def __init__(self, words_per_clock_cycle=1, skip_checksum=False): self.header = Signal(ipv4_header.length*8) - self.value = Signal(16) - self.done = Signal() + self.value = Signal(16) + self.done = Signal() # # # @@ -71,14 +71,11 @@ class LiteEthIPV4Checksum(Module): if not skip_checksum: n_cycles += 1 - counter = Signal(max=n_cycles+1) + counter = Signal(max=n_cycles+1) counter_ce = Signal() self.sync += If(counter_ce, counter.eq(counter + 1)) - - self.comb += [ - counter_ce.eq(~self.done), - self.done.eq(counter == n_cycles) - ] + self.comb += counter_ce.eq(~self.done) + self.comb += self.done.eq(counter == n_cycles) # IP TX -------------------------------------------------------------------------------------------- @@ -92,17 +89,15 @@ class LiteEthIPV4Packetizer(Packetizer): class LiteEthIPTX(Module): def __init__(self, mac_address, ip_address, arp_table, dw=8): - self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw)) + self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw)) self.source = source = stream.Endpoint(eth_mac_description(dw)) self.target_unreachable = Signal() # # # self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True) - self.comb += [ - checksum.ce.eq(sink.valid), - checksum.reset.eq(source.valid & source.last & source.ready) - ] + self.comb += checksum.ce.eq(sink.valid) + self.comb += checksum.reset.eq(source.valid & source.last & source.ready) self.submodules.packetizer = packetizer = LiteEthIPV4Packetizer(dw) self.comb += [ @@ -122,7 +117,7 @@ class LiteEthIPTX(Module): packetizer.sink.checksum.eq(checksum.value) ] - target_mac = Signal(48, reset_less=True) + target_mac = Signal(48, reset_less=True) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", @@ -186,7 +181,7 @@ class LiteEthIPV4Depacketizer(Depacketizer): class LiteEthIPRX(Module): def __init__(self, mac_address, ip_address, dw=8): - self.sink = sink = stream.Endpoint(eth_mac_description(dw)) + self.sink = sink = stream.Endpoint(eth_mac_description(dw)) self.source = source = stream.Endpoint(eth_ipv4_user_description(dw)) # # # diff --git a/liteeth/core/udp.py b/liteeth/core/udp.py index 869a63a..1f767f2 100644 --- a/liteeth/core/udp.py +++ b/liteeth/core/udp.py @@ -11,15 +11,15 @@ from litex.soc.interconnect.packet import Depacketizer, Packetizer class LiteEthUDPMasterPort: def __init__(self, dw): - self.dw = dw + self.dw = dw self.source = stream.Endpoint(eth_udp_user_description(dw)) - self.sink = stream.Endpoint(eth_udp_user_description(dw)) + self.sink = stream.Endpoint(eth_udp_user_description(dw)) class LiteEthUDPSlavePort: def __init__(self, dw): - self.dw = dw - self.sink = stream.Endpoint(eth_udp_user_description(dw)) + self.dw = dw + self.sink = stream.Endpoint(eth_udp_user_description(dw)) self.source = stream.Endpoint(eth_udp_user_description(dw)) @@ -37,7 +37,7 @@ class LiteEthUDPCrossbar(LiteEthCrossbar): if udp_port in self.users.keys(): raise ValueError("Port {0:#x} already assigned".format(udp_port)) - user_port = LiteEthUDPUserPort(dw) + user_port = LiteEthUDPUserPort(dw) internal_port = LiteEthUDPUserPort(self.dw) # tx @@ -49,8 +49,9 @@ class LiteEthUDPCrossbar(LiteEthCrossbar): self.comb += tx_stream.connect(tx_cdc.sink) tx_stream = tx_cdc.source if dw != self.dw: - tx_converter = stream.StrideConverter(eth_udp_user_description(user_port.dw), - eth_udp_user_description(self.dw)) + tx_converter = stream.StrideConverter( + eth_udp_user_description(user_port.dw), + eth_udp_user_description(self.dw)) self.submodules += tx_converter self.comb += tx_stream.connect(tx_converter.sink) tx_stream = tx_converter.source @@ -59,8 +60,9 @@ class LiteEthUDPCrossbar(LiteEthCrossbar): # rx rx_stream = internal_port.source if dw != self.dw: - rx_converter = stream.StrideConverter(eth_udp_user_description(self.dw), - eth_udp_user_description(user_port.dw)) + rx_converter = stream.StrideConverter( + eth_udp_user_description(self.dw), + eth_udp_user_description(user_port.dw)) self.submodules += rx_converter self.comb += rx_stream.connect(rx_converter.sink) rx_stream = rx_converter.source @@ -88,7 +90,7 @@ class LiteEthUDPPacketizer(Packetizer): class LiteEthUDPTX(Module): def __init__(self, ip_address, dw=8): - self.sink = sink = stream.Endpoint(eth_udp_user_description(dw)) + self.sink = sink = stream.Endpoint(eth_udp_user_description(dw)) self.source = source = stream.Endpoint(eth_ipv4_user_description(dw)) # # # @@ -135,7 +137,7 @@ class LiteEthUDPDepacketizer(Depacketizer): class LiteEthUDPRX(Module): def __init__(self, ip_address, dw=8): - self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw)) + self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw)) self.source = source = stream.Endpoint(eth_udp_user_description(dw)) # # #