From 306162096b28e872e7a5801cfe5a2ad7af0609c2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 8 Sep 2015 09:50:45 +0200 Subject: [PATCH] fix imports --- README | 6 +++--- doc/source/docs/getting_started/downloads.rst | 2 +- example_designs/make.py | 4 +++- example_designs/targets/base.py | 6 +++--- example_designs/targets/etherbone.py | 4 ++-- example_designs/targets/tty.py | 4 ++-- example_designs/targets/udp.py | 2 +- example_designs/test/make.py | 2 +- example_designs/test/test_etherbone.py | 2 +- liteeth/core/__init__.py | 12 ++++++------ liteeth/core/arp/__init__.py | 2 +- liteeth/core/icmp/__init__.py | 2 +- liteeth/core/ip/__init__.py | 6 +++--- liteeth/core/ip/checksum.py | 2 +- liteeth/core/ip/crossbar.py | 4 ++-- liteeth/core/mac/__init__.py | 8 ++++---- liteeth/core/mac/common.py | 4 ++-- liteeth/core/mac/core/__init__.py | 8 ++++---- liteeth/core/mac/core/crc.py | 2 +- liteeth/core/mac/core/gap.py | 2 +- liteeth/core/mac/core/last_be.py | 2 +- liteeth/core/mac/core/padding.py | 2 +- liteeth/core/mac/core/preamble.py | 2 +- liteeth/core/mac/frontend/sram.py | 2 +- liteeth/core/mac/frontend/wishbone.py | 4 ++-- liteeth/core/udp/__init__.py | 4 ++-- liteeth/core/udp/crossbar.py | 4 ++-- liteeth/crossbar.py | 2 +- liteeth/frontend/etherbone/__init__.py | 10 +++++----- liteeth/frontend/etherbone/packet.py | 2 +- liteeth/frontend/etherbone/probe.py | 2 +- liteeth/frontend/etherbone/record.py | 2 +- liteeth/frontend/etherbone/wishbone.py | 2 +- liteeth/frontend/tty.py | 2 +- liteeth/phy/__init__.py | 10 +++++----- liteeth/phy/gmii.py | 2 +- liteeth/phy/gmii_mii.py | 8 ++++---- liteeth/phy/loopback.py | 4 ++-- liteeth/phy/mii.py | 2 +- liteeth/phy/s6rgmii.py | 2 +- liteeth/phy/sim.py | 2 +- liteeth/software/wishbone.py | 2 +- test/arp_tb.py | 10 +++++----- test/common.py | 2 +- test/etherbone_tb.py | 10 +++++----- test/icmp_tb.py | 16 ++++++++-------- test/ip_tb.py | 8 ++++---- test/mac_core_tb.py | 8 ++++---- test/mac_wishbone_tb.py | 8 ++++---- test/model/arp.py | 10 +++++----- test/model/etherbone.py | 6 +++--- test/model/icmp.py | 12 ++++++------ test/model/ip.py | 10 +++++----- test/model/mac.py | 6 +++--- test/model/phy.py | 4 ++-- test/model/udp.py | 12 ++++++------ test/udp_tb.py | 8 ++++---- 57 files changed, 145 insertions(+), 143 deletions(-) diff --git a/README b/README index 5bbca60..df6de74 100644 --- a/README +++ b/README @@ -66,7 +66,7 @@ devel [AT] lists.m-labs.hk. git clone https://github.com/m-labs/misoc --recursive 4. Build and load UDP loopback design (only for KC705 for now): - go to misoclib/com/liteeth/example_designs/ + go to ./example_designs/ run ./make.py -t udp all load-bitstream 5. Test design (only for KC705 for now): @@ -83,7 +83,7 @@ devel [AT] lists.m-labs.hk. run ./make.py test_etherbone [> Simulations: - Simulations are available in misoclib/com/liteeth/test/: + Simulations are available in ./test/: - mac_core_tb - mac_wishbone_tb - arp_tb @@ -91,7 +91,7 @@ devel [AT] lists.m-labs.hk. - icmp_tb - udp_tb All ethernet layers have their own model tested against real ethernet dumps (dumps.py) - To run a simulation, move to misoclib/com/liteeth/test/ and run: + To run a simulation, move to ./test/ and run: make simulation_name [> Tests : diff --git a/doc/source/docs/getting_started/downloads.rst b/doc/source/docs/getting_started/downloads.rst index 0c2d3c0..358ec52 100644 --- a/doc/source/docs/getting_started/downloads.rst +++ b/doc/source/docs/getting_started/downloads.rst @@ -5,4 +5,4 @@ Download and install ==================== Please follow Getting started section of LiteEth README_. -.. _README: https://github.com/m-labs/misoc/blob/master/misoclib/com/liteeth/README +.. _README: https://github.com/enjoy-digital/liteeth/README diff --git a/example_designs/make.py b/example_designs/make.py index 023e857..724ab9e 100644 --- a/example_designs/make.py +++ b/example_designs/make.py @@ -16,7 +16,9 @@ from mibuild import tools from mibuild.xilinx.common import * from misoclib.soc import cpuif -from misoclib.com.liteeth.common import * +liteeth_path = "../" +sys.path.append(liteeth_path) # XXX +from liteeth.common import * def _import(default, name): diff --git a/example_designs/targets/base.py b/example_designs/targets/base.py index 3b8d9be..9be504b 100644 --- a/example_designs/targets/base.py +++ b/example_designs/targets/base.py @@ -10,9 +10,9 @@ from misoclib.tools.litescope.core.port import LiteScopeTerm from misoclib.com.uart.bridge import UARTWishboneBridge -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.phy import LiteEthPHY -from misoclib.com.liteeth.core import LiteEthUDPIPCore +from liteeth.common import * +from liteeth.phy import LiteEthPHY +from liteeth.core import LiteEthUDPIPCore class BaseSoC(SoC): diff --git a/example_designs/targets/etherbone.py b/example_designs/targets/etherbone.py index cf6dc51..fc36872 100644 --- a/example_designs/targets/etherbone.py +++ b/example_designs/targets/etherbone.py @@ -2,10 +2,10 @@ from misoclib.tools.litescope.common import * from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm -from misoclib.com.liteeth.common import * +from liteeth.common import * from targets.base import BaseSoC -from misoclib.com.liteeth.frontend.etherbone import LiteEthEtherbone +from liteeth.frontend.etherbone import LiteEthEtherbone class EtherboneSoC(BaseSoC): diff --git a/example_designs/targets/tty.py b/example_designs/targets/tty.py index fc51330..757e845 100644 --- a/example_designs/targets/tty.py +++ b/example_designs/targets/tty.py @@ -2,10 +2,10 @@ from misoclib.tools.litescope.common import * from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm -from misoclib.com.liteeth.common import * +from liteeth.common import * from targets.base import BaseSoC -from misoclib.com.liteeth.frontend.tty import LiteEthTTY +from liteeth.frontend.tty import LiteEthTTY class TTYSoC(BaseSoC): diff --git a/example_designs/targets/udp.py b/example_designs/targets/udp.py index c793f2a..71bb883 100644 --- a/example_designs/targets/udp.py +++ b/example_designs/targets/udp.py @@ -2,7 +2,7 @@ from misoclib.tools.litescope.common import * from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm -from misoclib.com.liteeth.common import * +from liteeth.common import * from targets.base import BaseSoC diff --git a/example_designs/test/make.py b/example_designs/test/make.py index bfab18c..1ac8314 100644 --- a/example_designs/test/make.py +++ b/example_designs/test/make.py @@ -23,7 +23,7 @@ if __name__ == "__main__": port = args.port if not args.port.isdigit() else int(args.port) wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False) elif args.bridge == "etherbone": - from misoclib.com.liteeth.software.wishbone import LiteETHWishboneBridgeDriver + from liteeth.software.wishbone import LiteETHWishboneBridgeDriver wb = LiteETHWishboneBridgeDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False) else: ValueError("Invalid bridge {}".format(args.bridge)) diff --git a/example_designs/test/test_etherbone.py b/example_designs/test/test_etherbone.py index adfbf1a..ee6290e 100644 --- a/example_designs/test/test_etherbone.py +++ b/example_designs/test/test_etherbone.py @@ -1,6 +1,6 @@ import socket import time -from misoclib.com.liteeth.test.model.etherbone import * +from liteeth.test.model.etherbone import * SRAM_BASE = 0x02000000 diff --git a/liteeth/core/__init__.py b/liteeth/core/__init__.py index 176e6b1..20689a7 100644 --- a/liteeth/core/__init__.py +++ b/liteeth/core/__init__.py @@ -1,9 +1,9 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core.mac import LiteEthMAC -from misoclib.com.liteeth.core.arp import LiteEthARP -from misoclib.com.liteeth.core.ip import LiteEthIP -from misoclib.com.liteeth.core.udp import LiteEthUDP -from misoclib.com.liteeth.core.icmp import LiteEthICMP +from liteeth.common import * +from liteeth.core.mac import LiteEthMAC +from liteeth.core.arp import LiteEthARP +from liteeth.core.ip import LiteEthIP +from liteeth.core.udp import LiteEthUDP +from liteeth.core.icmp import LiteEthICMP class LiteEthIPCore(Module, AutoCSR): diff --git a/liteeth/core/arp/__init__.py b/liteeth/core/arp/__init__.py index a0f26c5..bfce79e 100644 --- a/liteeth/core/arp/__init__.py +++ b/liteeth/core/arp/__init__.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * _arp_table_layout = [ ("reply", 1), diff --git a/liteeth/core/icmp/__init__.py b/liteeth/core/icmp/__init__.py index fc3bdff..b72e018 100644 --- a/liteeth/core/icmp/__init__.py +++ b/liteeth/core/icmp/__init__.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthICMPPacketizer(Packetizer): diff --git a/liteeth/core/ip/__init__.py b/liteeth/core/ip/__init__.py index db564aa..a181e0f 100644 --- a/liteeth/core/ip/__init__.py +++ b/liteeth/core/ip/__init__.py @@ -1,6 +1,6 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core.ip.checksum import * -from misoclib.com.liteeth.core.ip.crossbar import * +from liteeth.common import * +from liteeth.core.ip.checksum import * +from liteeth.core.ip.crossbar import * class LiteEthIPV4Packetizer(Packetizer): diff --git a/liteeth/core/ip/checksum.py b/liteeth/core/ip/checksum.py index 34e8467..1faa171 100644 --- a/liteeth/core/ip/checksum.py +++ b/liteeth/core/ip/checksum.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthIPV4Checksum(Module): diff --git a/liteeth/core/ip/crossbar.py b/liteeth/core/ip/crossbar.py index 4570f4f..fa634c2 100644 --- a/liteeth/core/ip/crossbar.py +++ b/liteeth/core/ip/crossbar.py @@ -1,5 +1,5 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.crossbar import LiteEthCrossbar +from liteeth.common import * +from liteeth.crossbar import LiteEthCrossbar class LiteEthIPV4MasterPort: diff --git a/liteeth/core/mac/__init__.py b/liteeth/core/mac/__init__.py index acb226d..dd1fb3f 100644 --- a/liteeth/core/mac/__init__.py +++ b/liteeth/core/mac/__init__.py @@ -1,7 +1,7 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core.mac.common import * -from misoclib.com.liteeth.core.mac.core import LiteEthMACCore -from misoclib.com.liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface +from liteeth.common import * +from liteeth.core.mac.common import * +from liteeth.core.mac.core import LiteEthMACCore +from liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface class LiteEthMAC(Module, AutoCSR): diff --git a/liteeth/core/mac/common.py b/liteeth/core/mac/common.py index f12cc3e..64d6424 100644 --- a/liteeth/core/mac/common.py +++ b/liteeth/core/mac/common.py @@ -1,5 +1,5 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.crossbar import LiteEthCrossbar +from liteeth.common import * +from liteeth.crossbar import LiteEthCrossbar class LiteEthMACDepacketizer(Depacketizer): diff --git a/liteeth/core/mac/core/__init__.py b/liteeth/core/mac/core/__init__.py index fdf50b8..7a56715 100644 --- a/liteeth/core/mac/core/__init__.py +++ b/liteeth/core/mac/core/__init__.py @@ -1,7 +1,7 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be -from misoclib.com.liteeth.phy.sim import LiteEthPHYSim -from misoclib.com.liteeth.phy.mii import LiteEthPHYMII +from liteeth.common import * +from liteeth.core.mac.core import gap, preamble, crc, padding, last_be +from liteeth.phy.sim import LiteEthPHYSim +from liteeth.phy.mii import LiteEthPHYMII class LiteEthMACCore(Module, AutoCSR): diff --git a/liteeth/core/mac/core/crc.py b/liteeth/core/mac/core/crc.py index f08302b..4765aa7 100644 --- a/liteeth/core/mac/core/crc.py +++ b/liteeth/core/mac/core/crc.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthMACCRCEngine(Module): diff --git a/liteeth/core/mac/core/gap.py b/liteeth/core/mac/core/gap.py index c1bd916..9935304 100644 --- a/liteeth/core/mac/core/gap.py +++ b/liteeth/core/mac/core/gap.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthMACGap(Module): def __init__(self, dw, ack_on_gap=False): diff --git a/liteeth/core/mac/core/last_be.py b/liteeth/core/mac/core/last_be.py index 42f7c64..26a00b3 100644 --- a/liteeth/core/mac/core/last_be.py +++ b/liteeth/core/mac/core/last_be.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthMACTXLastBE(Module): diff --git a/liteeth/core/mac/core/padding.py b/liteeth/core/mac/core/padding.py index 38b2a3d..5962f76 100644 --- a/liteeth/core/mac/core/padding.py +++ b/liteeth/core/mac/core/padding.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthMACPaddingInserter(Module): diff --git a/liteeth/core/mac/core/preamble.py b/liteeth/core/mac/core/preamble.py index e4d7346..2160c0c 100644 --- a/liteeth/core/mac/core/preamble.py +++ b/liteeth/core/mac/core/preamble.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthMACPreambleInserter(Module): diff --git a/liteeth/core/mac/frontend/sram.py b/liteeth/core/mac/frontend/sram.py index fc3d8c2..6482359 100644 --- a/liteeth/core/mac/frontend/sram.py +++ b/liteeth/core/mac/frontend/sram.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * from migen.bank.description import * from migen.bank.eventmanager import * diff --git a/liteeth/core/mac/frontend/wishbone.py b/liteeth/core/mac/frontend/wishbone.py index 48a8f1d..d39a671 100644 --- a/liteeth/core/mac/frontend/wishbone.py +++ b/liteeth/core/mac/frontend/wishbone.py @@ -1,5 +1,5 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core.mac.frontend import sram +from liteeth.common import * +from liteeth.core.mac.frontend import sram from migen.bus import wishbone from migen.fhdl.simplify import FullMemoryWE diff --git a/liteeth/core/udp/__init__.py b/liteeth/core/udp/__init__.py index b0f02d5..4897a8e 100644 --- a/liteeth/core/udp/__init__.py +++ b/liteeth/core/udp/__init__.py @@ -1,5 +1,5 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core.udp.crossbar import * +from liteeth.common import * +from liteeth.core.udp.crossbar import * class LiteEthUDPPacketizer(Packetizer): diff --git a/liteeth/core/udp/crossbar.py b/liteeth/core/udp/crossbar.py index 16b2b20..247d789 100644 --- a/liteeth/core/udp/crossbar.py +++ b/liteeth/core/udp/crossbar.py @@ -1,5 +1,5 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.crossbar import LiteEthCrossbar +from liteeth.common import * +from liteeth.crossbar import LiteEthCrossbar class LiteEthUDPMasterPort: diff --git a/liteeth/crossbar.py b/liteeth/crossbar.py index d2ee22d..bf61ec4 100644 --- a/liteeth/crossbar.py +++ b/liteeth/crossbar.py @@ -1,6 +1,6 @@ from collections import OrderedDict -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthCrossbar(Module): def __init__(self, master_port, dispatch_param): diff --git a/liteeth/frontend/etherbone/__init__.py b/liteeth/frontend/etherbone/__init__.py index 0f7d586..56a00cf 100644 --- a/liteeth/frontend/etherbone/__init__.py +++ b/liteeth/frontend/etherbone/__init__.py @@ -1,8 +1,8 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.frontend.etherbone.packet import * -from misoclib.com.liteeth.frontend.etherbone.probe import * -from misoclib.com.liteeth.frontend.etherbone.record import * -from misoclib.com.liteeth.frontend.etherbone.wishbone import * +from liteeth.common import * +from liteeth.frontend.etherbone.packet import * +from liteeth.frontend.etherbone.probe import * +from liteeth.frontend.etherbone.record import * +from liteeth.frontend.etherbone.wishbone import * class LiteEthEtherbone(Module): diff --git a/liteeth/frontend/etherbone/packet.py b/liteeth/frontend/etherbone/packet.py index e628bd9..36cde5e 100644 --- a/liteeth/frontend/etherbone/packet.py +++ b/liteeth/frontend/etherbone/packet.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthEtherbonePacketPacketizer(Packetizer): diff --git a/liteeth/frontend/etherbone/probe.py b/liteeth/frontend/etherbone/probe.py index ade1305..24a4d8b 100644 --- a/liteeth/frontend/etherbone/probe.py +++ b/liteeth/frontend/etherbone/probe.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthEtherboneProbe(Module): diff --git a/liteeth/frontend/etherbone/record.py b/liteeth/frontend/etherbone/record.py index 15879fd..ca81ac5 100644 --- a/liteeth/frontend/etherbone/record.py +++ b/liteeth/frontend/etherbone/record.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthEtherboneRecordPacketizer(Packetizer): diff --git a/liteeth/frontend/etherbone/wishbone.py b/liteeth/frontend/etherbone/wishbone.py index b9b8c3b..3c18e3b 100644 --- a/liteeth/frontend/etherbone/wishbone.py +++ b/liteeth/frontend/etherbone/wishbone.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * from migen.bus import wishbone diff --git a/liteeth/frontend/tty.py b/liteeth/frontend/tty.py index 56867af..ad2d07b 100644 --- a/liteeth/frontend/tty.py +++ b/liteeth/frontend/tty.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthTTYTX(Module): diff --git a/liteeth/phy/__init__.py b/liteeth/phy/__init__.py index d2fbe64..1f732c1 100644 --- a/liteeth/phy/__init__.py +++ b/liteeth/phy/__init__.py @@ -1,27 +1,27 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs): # Autodetect PHY if hasattr(pads, "source_stb"): # This is a simulation PHY - from misoclib.com.liteeth.phy.sim import LiteEthPHYSim + from liteeth.phy.sim import LiteEthPHYSim return LiteEthPHYSim(pads) elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8: if hasattr(clock_pads, "tx"): # This is a 10/100/1G PHY - from misoclib.com.liteeth.phy.gmii_mii import LiteEthPHYGMIIMII + from liteeth.phy.gmii_mii import LiteEthPHYGMIIMII return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs) else: # This is a pure 1G PHY - from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII + from liteeth.phy.gmii import LiteEthPHYGMII return LiteEthPHYGMII(clock_pads, pads, **kwargs) elif hasattr(pads, "rx_ctl"): # This is a 10/100/1G RGMII PHY raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation") elif flen(pads.tx_data) == 4: # This is a MII PHY - from misoclib.com.liteeth.phy.mii import LiteEthPHYMII + from liteeth.phy.mii import LiteEthPHYMII return LiteEthPHYMII(clock_pads, pads, **kwargs) else: raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation") diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index cdf0718..7626714 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -1,6 +1,6 @@ from migen.genlib.io import DDROutput -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthPHYGMIITX(Module): diff --git a/liteeth/phy/gmii_mii.py b/liteeth/phy/gmii_mii.py index ec3e585..5a17b5c 100644 --- a/liteeth/phy/gmii_mii.py +++ b/liteeth/phy/gmii_mii.py @@ -2,11 +2,11 @@ from migen.genlib.io import DDROutput from migen.flow.plumbing import Multiplexer, Demultiplexer from migen.genlib.cdc import PulseSynchronizer -from misoclib.com.liteeth.common import * +from liteeth.common import * -from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIICRG -from misoclib.com.liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX -from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX +from liteeth.phy.gmii import LiteEthPHYGMIICRG +from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX +from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX modes = { "GMII": 0, diff --git a/liteeth/phy/loopback.py b/liteeth/phy/loopback.py index 1d21400..abdb936 100644 --- a/liteeth/phy/loopback.py +++ b/liteeth/phy/loopback.py @@ -1,5 +1,5 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * +from liteeth.common import * +from liteeth.generic import * class LiteEthPHYLoopbackCRG(Module, AutoCSR): diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py index e687e76..6b2faec 100644 --- a/liteeth/phy/mii.py +++ b/liteeth/phy/mii.py @@ -1,4 +1,4 @@ -from misoclib.com.liteeth.common import * +from liteeth.common import * def converter_description(dw): diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index dc25ea7..60e6d83 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -4,7 +4,7 @@ from migen.genlib.io import DDROutput from migen.genlib.misc import WaitTimer from migen.genlib.fsm import FSM, NextState -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthPHYRGMIITX(Module): diff --git a/liteeth/phy/sim.py b/liteeth/phy/sim.py index eda52d6..26e69f0 100644 --- a/liteeth/phy/sim.py +++ b/liteeth/phy/sim.py @@ -1,6 +1,6 @@ import os -from misoclib.com.liteeth.common import * +from liteeth.common import * class LiteEthPHYSimCRG(Module, AutoCSR): diff --git a/liteeth/software/wishbone.py b/liteeth/software/wishbone.py index 04a8563..f9ded24 100644 --- a/liteeth/software/wishbone.py +++ b/liteeth/software/wishbone.py @@ -2,7 +2,7 @@ import socket from misoclib.tools.litescope.software.driver.reg import * -from misoclib.com.liteeth.test.model.etherbone import * +from liteeth.test.model.etherbone import * class LiteEthWishboneBridgeDriver: diff --git a/test/arp_tb.py b/test/arp_tb.py index 0856450..00e7b1e 100644 --- a/test/arp_tb.py +++ b/test/arp_tb.py @@ -3,12 +3,12 @@ from migen.bus import wishbone from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core.mac import LiteEthMAC -from misoclib.com.liteeth.core.arp import LiteEthARP +from liteeth.common import * +from liteeth.core.mac import LiteEthMAC +from liteeth.core.arp import LiteEthARP -from misoclib.com.liteeth.test.common import * -from misoclib.com.liteeth.test.model import phy, mac, arp +from liteeth.test.common import * +from liteeth.test.model import phy, mac, arp ip_address = 0x12345678 mac_address = 0x12345678abcd diff --git a/test/common.py b/test/common.py index 716443c..e26426c 100644 --- a/test/common.py +++ b/test/common.py @@ -5,7 +5,7 @@ from migen.fhdl.std import * from migen.flow.actor import Sink, Source from migen.genlib.record import * -from misoclib.com.liteeth.common import * +from liteeth.common import * def print_with_prefix(s, prefix=""): diff --git a/test/etherbone_tb.py b/test/etherbone_tb.py index 8f86847..1e20de2 100644 --- a/test/etherbone_tb.py +++ b/test/etherbone_tb.py @@ -3,12 +3,12 @@ from migen.bus import wishbone from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core import LiteEthUDPIPCore -from misoclib.com.liteeth.frontend.etherbone import LiteEthEtherbone +from liteeth.common import * +from liteeth.core import LiteEthUDPIPCore +from liteeth.frontend.etherbone import LiteEthEtherbone -from misoclib.com.liteeth.test.common import * -from misoclib.com.liteeth.test.model import phy, mac, arp, ip, udp, etherbone +from liteeth.test.common import * +from liteeth.test.model import phy, mac, arp, ip, udp, etherbone ip_address = 0x12345678 mac_address = 0x12345678abcd diff --git a/test/icmp_tb.py b/test/icmp_tb.py index 5802717..8c9f211 100644 --- a/test/icmp_tb.py +++ b/test/icmp_tb.py @@ -3,15 +3,15 @@ from migen.bus import wishbone from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core import LiteEthIPCore +from liteeth.common import * +from liteeth.core import LiteEthIPCore -from misoclib.com.liteeth.test.common import * -from misoclib.com.liteeth.test.model.dumps import * -from misoclib.com.liteeth.test.model.mac import * -from misoclib.com.liteeth.test.model.ip import * -from misoclib.com.liteeth.test.model.icmp import * -from misoclib.com.liteeth.test.model import phy, mac, arp, ip, icmp +from liteeth.test.common import * +from liteeth.test.model.dumps import * +from liteeth.test.model.mac import * +from liteeth.test.model.ip import * +from liteeth.test.model.icmp import * +from liteeth.test.model import phy, mac, arp, ip, icmp ip_address = 0x12345678 mac_address = 0x12345678abcd diff --git a/test/ip_tb.py b/test/ip_tb.py index 1275b59..01ba1ba 100644 --- a/test/ip_tb.py +++ b/test/ip_tb.py @@ -3,11 +3,11 @@ from migen.bus import wishbone from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core import LiteEthIPCore +from liteeth.common import * +from liteeth.core import LiteEthIPCore -from misoclib.com.liteeth.test.common import * -from misoclib.com.liteeth.test.model import phy, mac, arp, ip +from liteeth.test.common import * +from liteeth.test.model import phy, mac, arp, ip ip_address = 0x12345678 mac_address = 0x12345678abcd diff --git a/test/mac_core_tb.py b/test/mac_core_tb.py index c7afdc2..5cfea8e 100644 --- a/test/mac_core_tb.py +++ b/test/mac_core_tb.py @@ -3,11 +3,11 @@ from migen.bus import wishbone from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core.mac.core import LiteEthMACCore +from liteeth.common import * +from liteeth.core.mac.core import LiteEthMACCore -from misoclib.com.liteeth.test.common import * -from misoclib.com.liteeth.test.model import phy, mac +from liteeth.test.common import * +from liteeth.test.model import phy, mac class TB(Module): diff --git a/test/mac_wishbone_tb.py b/test/mac_wishbone_tb.py index 19e7b66..cdad897 100644 --- a/test/mac_wishbone_tb.py +++ b/test/mac_wishbone_tb.py @@ -3,11 +3,11 @@ from migen.bus import wishbone from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core.mac import LiteEthMAC +from liteeth.common import * +from liteeth.core.mac import LiteEthMAC -from misoclib.com.liteeth.test.common import * -from misoclib.com.liteeth.test.model import phy, mac +from liteeth.test.common import * +from liteeth.test.model import phy, mac class WishboneMaster: diff --git a/test/model/arp.py b/test/model/arp.py index 9a58fea..f9bc511 100644 --- a/test/model/arp.py +++ b/test/model/arp.py @@ -1,9 +1,9 @@ import math -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.test.common import * +from liteeth.common import * +from liteeth.test.common import * -from misoclib.com.liteeth.test.model import mac +from liteeth.test.model import mac def print_arp(s): @@ -123,8 +123,8 @@ class ARP(Module): request.target_ip = ip_address if __name__ == "__main__": - from misoclib.com.liteeth.test.model.dumps import * - from misoclib.com.liteeth.test.model.mac import * + from liteeth.test.model.dumps import * + from liteeth.test.model.mac import * errors = 0 # ARP request packet = MACPacket(arp_request) diff --git a/test/model/etherbone.py b/test/model/etherbone.py index 4f3f558..170c030 100644 --- a/test/model/etherbone.py +++ b/test/model/etherbone.py @@ -1,10 +1,10 @@ import math import copy -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.test.common import * +from liteeth.common import * +from liteeth.test.common import * -from misoclib.com.liteeth.test.model import udp +from liteeth.test.model import udp def print_etherbone(s): diff --git a/test/model/icmp.py b/test/model/icmp.py index 48dc073..ae1a6e7 100644 --- a/test/model/icmp.py +++ b/test/model/icmp.py @@ -1,9 +1,9 @@ import math -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.test.common import * +from liteeth.common import * +from liteeth.test.common import * -from misoclib.com.liteeth.test.model import ip +from liteeth.test.model import ip def print_icmp(s): @@ -84,9 +84,9 @@ class ICMP(Module): pass if __name__ == "__main__": - from misoclib.com.liteeth.test.model.dumps import * - from misoclib.com.liteeth.test.model.mac import * - from misoclib.com.liteeth.test.model.ip import * + from liteeth.test.model.dumps import * + from liteeth.test.model.mac import * + from liteeth.test.model.ip import * errors = 0 # ICMP packet packet = MACPacket(ping_request) diff --git a/test/model/ip.py b/test/model/ip.py index 6703087..2c195a3 100644 --- a/test/model/ip.py +++ b/test/model/ip.py @@ -1,9 +1,9 @@ import math -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.test.common import * +from liteeth.common import * +from liteeth.test.common import * -from misoclib.com.liteeth.test.model import mac +from liteeth.test.model import mac def print_ip(s): @@ -131,8 +131,8 @@ class IP(Module): self.icmp_callback(packet) if __name__ == "__main__": - from misoclib.com.liteeth.test.model.dumps import * - from misoclib.com.liteeth.test.model.mac import * + from liteeth.test.model.dumps import * + from liteeth.test.model.mac import * errors = 0 # UDP packet packet = MACPacket(udp) diff --git a/test/model/mac.py b/test/model/mac.py index 6697121..f15b60a 100644 --- a/test/model/mac.py +++ b/test/model/mac.py @@ -1,8 +1,8 @@ import math import binascii -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.test.common import * +from liteeth.common import * +from liteeth.test.common import * def print_mac(s): @@ -134,7 +134,7 @@ class MAC(Module): raise ValueError # XXX handle this properly if __name__ == "__main__": - from misoclib.com.liteeth.test.model.dumps import * + from liteeth.test.model.dumps import * errors = 0 packet = MACPacket(arp_request) packet.decode_remove_header() diff --git a/test/model/phy.py b/test/model/phy.py index 0bc2908..1952bde 100644 --- a/test/model/phy.py +++ b/test/model/phy.py @@ -1,5 +1,5 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.test.common import * +from liteeth.common import * +from liteeth.test.common import * def print_phy(s): diff --git a/test/model/udp.py b/test/model/udp.py index 6c6a2bd..9640a9d 100644 --- a/test/model/udp.py +++ b/test/model/udp.py @@ -1,9 +1,9 @@ import math -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.test.common import * +from liteeth.common import * +from liteeth.test.common import * -from misoclib.com.liteeth.test.model import ip +from liteeth.test.model import ip def print_udp(s): @@ -95,9 +95,9 @@ class UDP(Module): self.etherbone_callback(packet) if __name__ == "__main__": - from misoclib.com.liteeth.test.model.dumps import * - from misoclib.com.liteeth.test.model.mac import * - from misoclib.com.liteeth.test.model.ip import * + from liteeth.test.model.dumps import * + from liteeth.test.model.mac import * + from liteeth.test.model.ip import * errors = 0 # UDP packet packet = MACPacket(udp) diff --git a/test/udp_tb.py b/test/udp_tb.py index c7e04c8..8caf4cf 100644 --- a/test/udp_tb.py +++ b/test/udp_tb.py @@ -3,11 +3,11 @@ from migen.bus import wishbone from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.core import LiteEthUDPIPCore +from liteeth.common import * +from liteeth.core import LiteEthUDPIPCore -from misoclib.com.liteeth.test.common import * -from misoclib.com.liteeth.test.model import phy, mac, arp, ip, udp +from liteeth.test.common import * +from liteeth.test.model import phy, mac, arp, ip, udp ip_address = 0x12345678 mac_address = 0x12345678abcd