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mac/crc/LiteEthMACCRC32: Avoid multiple XORs/Checks on output.

This commit is contained in:
Florent Kermarrec 2024-04-04 16:39:32 +02:00
parent 3e8103996f
commit 30e66a7e21
1 changed files with 18 additions and 12 deletions
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30
liteeth/mac/crc.py
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@ -95,13 +95,13 @@ class LiteEthMACCRC32(LiteXModule):
""" """
width = 32 width = 32
polynom = 0x04c11db7 polynom = 0x04c11db7
init = 2**width-1 init = 2**width - 1
check = 0xc704dd7b check = 0xc704dd7b
def __init__(self, data_width): def __init__(self, data_width):
self.data = Signal(data_width) self.data = Signal(data_width)
self.be = Signal(data_width//8, reset=2**data_width//8 - 1) self.be = Signal(data_width//8, reset=2**data_width//8 - 1)
self.value = Signal(self.width) self.value = Signal(self.width)
self.error = Signal() self.error = Signal()
# # # # # #
@ -117,16 +117,22 @@ class LiteEthMACCRC32(LiteXModule):
self.sync += reg.eq(engines[-1].crc_next) self.sync += reg.eq(engines[-1].crc_next)
# Select CRC Engine/Result. # Select CRC Engine/Result.
crc_next = Signal(self.width)
for n in range(data_width//8): for n in range(data_width//8):
self.comb += [ self.comb += [
engines[n].data.eq(self.data[:(n + 1)*8]), engines[n].data.eq(self.data),
engines[n].crc_prev.eq(reg), engines[n].crc_prev.eq(reg),
If(self.be[n], If(self.be[n],
self.value.eq(reverse_bits(~engines[n].crc_next)), crc_next.eq(engines[n].crc_next)
self.error.eq(engines[n].crc_next != self.check),
) )
] ]
# Output.
self.comb += [
self.value.eq(crc_next[::-1] ^ self.init),
self.error.eq(crc_next != self.check),
]
# MAC CRC32 Inserter ------------------------------------------------------------------------------- # MAC CRC32 Inserter -------------------------------------------------------------------------------
class LiteEthMACCRC32Inserter(LiteXModule): class LiteEthMACCRC32Inserter(LiteXModule):
@ -163,6 +169,10 @@ class LiteEthMACCRC32Inserter(LiteXModule):
# CRC32 Generator. # CRC32 Generator.
self.crc = crc = LiteEthMACCRC32(data_width) self.crc = crc = LiteEthMACCRC32(data_width)
self.comb += [
crc.data.eq(sink.data),
crc.be.eq(sink.last_be),
]
# FSM. # FSM.
self.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
@ -174,10 +184,6 @@ class LiteEthMACCRC32Inserter(LiteXModule):
NextState("COPY"), NextState("COPY"),
) )
) )
self.comb += [
crc.data.eq(sink.data),
crc.be.eq(sink.last_be),
]
fsm.act("COPY", fsm.act("COPY",
crc.ce.eq(sink.valid & source.ready), crc.ce.eq(sink.valid & source.ready),
sink.connect(source), sink.connect(source),