Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

mac/crc/LiteEthMACCRC32: Avoid multiple XORs/Checks on output.

This commit is contained in:
Florent Kermarrec 2024-04-04 16:39:32 +02:00
parent 3e8103996f
commit 30e66a7e21
1 changed files with 18 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
liteeth/mac/crc.py
View File

@ -117,16 +117,22 @@ class LiteEthMACCRC32(LiteXModule):
self.sync += reg.eq(engines[-1].crc_next)
# Select CRC Engine/Result.
crc_next = Signal(self.width)
for n in range(data_width//8):
self.comb += [
engines[n].data.eq(self.data[:(n + 1)*8]),
engines[n].data.eq(self.data),
engines[n].crc_prev.eq(reg),
If(self.be[n],
self.value.eq(reverse_bits(~engines[n].crc_next)),
self.error.eq(engines[n].crc_next != self.check),
crc_next.eq(engines[n].crc_next)
)
]
# Output.
self.comb += [
self.value.eq(crc_next[::-1] ^ self.init),
self.error.eq(crc_next != self.check),
]
# MAC CRC32 Inserter -------------------------------------------------------------------------------
class LiteEthMACCRC32Inserter(LiteXModule):
@ -163,6 +169,10 @@ class LiteEthMACCRC32Inserter(LiteXModule):
# CRC32 Generator.
self.crc = crc = LiteEthMACCRC32(data_width)
self.comb += [
crc.data.eq(sink.data),
crc.be.eq(sink.last_be),
]
# FSM.
self.fsm = fsm = FSM(reset_state="IDLE")
@ -174,10 +184,6 @@ class LiteEthMACCRC32Inserter(LiteXModule):
NextState("COPY"),
)
)
self.comb += [
crc.data.eq(sink.data),
crc.be.eq(sink.last_be),
]
fsm.act("COPY",
crc.ce.eq(sink.valid & source.ready),
sink.connect(source),