phy/pcs_1000basex: Simplify/Cleanup PCSTX.
This commit is contained in:
Florent Kermarrec
parent
8a3e0a23aa
commit
313e7a985c
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@ -19,128 +19,120 @@ from litex.soc.cores.code_8b10b import K, D, Encoder, Decoder
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from liteeth.common import *
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# Constants / Helpers ------------------------------------------------------------------------------
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SGMII_1000MBPS_SPEED = 0b10
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SGMII_100MBPS_SPEED = 0b01
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SGMII_10MBPS_SPEED = 0b00
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CTYPE_C1 = 0b0
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CTYPE_C2 = 0b1
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ITYPE_I1 = 0b0
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ITYPË_I2 = 0b1
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# PCS TX -------------------------------------------------------------------------------------------
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class PCSTX(LiteXModule):
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def __init__(self, lsb_first=False):
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self.config_valid = Signal()
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self.config_reg = Signal(16)
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self.tx_valid = Signal()
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self.tx_ready = Signal()
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self.tx_data = Signal(8)
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self.config_reg = Signal(16) # Config register (16-bit).
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self.sgmii_speed = Signal(2) # SGMII speed.
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self.sink = sink = stream.Endpoint([("data", 8)]) # Data input.
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self.encoder = Encoder(lsb_first=lsb_first)
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self.encoder = Encoder(lsb_first=lsb_first) # 8b/10b encoder.
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# SGMII Speed Adaptation
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self.sgmii_speed = Signal(2)
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# Signals.
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# --------
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count = Signal() # Byte counter for config register.
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parity = Signal() # Parity for /R/ extension.
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ctype = Signal() # Toggles config type.
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# # #
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parity = Signal()
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c_type = Signal()
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self.sync += parity.eq(~parity)
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config_reg_buffer = Signal(16)
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load_config_reg_buffer = Signal()
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self.sync += If(load_config_reg_buffer, config_reg_buffer.eq(self.config_reg))
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# Timer for SGMII data rates.
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timer = Signal(max=1000)
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timer_en = Signal()
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# SGMII timer.
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# ------------
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timer = Signal(max=100)
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timer_done = Signal()
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timer_enable = Signal()
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self.comb += timer_done.eq(timer == 0)
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self.sync += [
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If(~timer_en | (timer == 0),
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timer.eq(timer - 1),
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If(~timer_enable | timer_done,
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Case(self.sgmii_speed, {
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0b00: timer.eq(99),
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0b01: timer.eq( 9),
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0b10: timer.eq( 0),
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SGMII_10MBPS_SPEED : timer.eq(99),
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SGMII_100MBPS_SPEED : timer.eq(9),
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SGMII_1000MBPS_SPEED : timer.eq(0),
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})
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).Elif(timer_en,
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timer.eq(timer - 1)
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)
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]
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# FSM.
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# ----
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self.fsm = fsm = FSM()
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fsm.act("START",
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If(self.config_valid,
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self.tx_ready.eq(1), # Discard TX data if we are in config_reg phase.
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load_config_reg_buffer.eq(1),
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(28, 5)),
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NextState("CONFIG_D")
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NextValue(count, 0),
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NextState("CONFIG-D")
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).Else(
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If(self.tx_valid,
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# The first byte sent is replaced by /S/.
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self.tx_ready.eq((timer == 0)),
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timer_en.eq(1),
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If(sink.valid,
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(27, 7)),
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self.encoder.d[0].eq(K(27, 7)), # Start-of-packet /S/.
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NextState("DATA")
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).Else(
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self.tx_ready.eq(1), # Discard TX data.
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(28, 5)),
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NextState("IDLE")
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)
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)
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)
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fsm.act("CONFIG_D",
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If(c_type,
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self.encoder.d[0].eq(D(2, 2))
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).Else(
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self.encoder.d[0].eq(D(21, 5))
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fsm.act("CONFIG-D",
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# Send Configuration Word.
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Case(ctype, {
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CTYPE_C1 : self.encoder.d[0].eq(D(21, 5)), # C1.
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CTYPE_C2 : self.encoder.d[0].eq(D( 2, 2)), # C2.
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}),
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NextValue(ctype, ~ctype),
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NextState("CONFIG-REG")
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),
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NextValue(c_type, ~c_type),
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NextState("CONFIG_REG_LSB")
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),
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fsm.act("CONFIG_REG_LSB",
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self.encoder.d[0].eq(config_reg_buffer[:8]),
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NextState("CONFIG_REG_MSB")
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)
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fsm.act("CONFIG_REG_MSB",
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self.encoder.d[0].eq(config_reg_buffer[8:]),
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NextState("START")
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fsm.act("CONFIG-REG",
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# Send Configuration Register.
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NextValue(count, count + 1),
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Case(count, {
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0 : self.encoder.d[0].eq(self.config_reg[:8]), # LSB.
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1 : self.encoder.d[0].eq(self.config_reg[8:]), # MSB.
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}),
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If(count == (2 - 1), NextState("START"))
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)
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fsm.act("IDLE",
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# Due to latency in the encoder, we read here the disparity
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# just before the K28.5 was sent. K28.5 flips the disparity.
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If(self.encoder.disparity[0],
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# Correcting /I1/ (D5.6 preserves the disparity).
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self.encoder.d[0].eq(D(5, 6))
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).Else(
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# Preserving /I2/ (D16.2 flips the disparity).
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self.encoder.d[0].eq(D(16, 2))
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),
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# Send Idle characters and handle disparity.
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Case(self.encoder.disparity[0], {
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ITYPE_I1 : self.encoder.d[0].eq(D(5, 6)), # /I1/ preserves disparity.
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ITYPË_I2 : self.encoder.d[0].eq(D(16, 2)), # /I2/ flips disparity.
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}),
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NextState("START")
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)
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fsm.act("DATA",
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If(self.tx_valid,
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self.tx_ready.eq((timer == 0)),
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timer_en.eq(1),
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self.encoder.d[0].eq(self.tx_data)
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# Send Data frame.
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timer_enable.eq(1),
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sink.ready.eq(timer_done),
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If(sink.valid,
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self.encoder.d[0].eq(sink.data),
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).Else(
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self.tx_ready.eq(1),
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# /T/
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(29, 7)),
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NextState("CARRIER_EXTEND_1")
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self.encoder.d[0].eq(K(29, 7)), # End-of-frame /T/.
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NextState("CARRIER-EXTEND")
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)
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)
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fsm.act("CARRIER_EXTEND_1",
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# /R/
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fsm.act("CARRIER-EXTEND",
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# Extend carrier with /R/ symbols.
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(23, 7)),
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self.encoder.d[0].eq(K(23, 7)), # Carrier Extend /R/.
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If(parity,
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NextState("START")
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).Else(
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NextState("CARRIER_EXTEND_2")
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)
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)
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fsm.act("CARRIER_EXTEND_2",
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# /R/
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(23, 7)),
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NextState("START")
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)
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self.sync += parity.eq(~parity) # Toggle parity for /R/ extension.
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# PCS RX -------------------------------------------------------------------------------------------
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@ -178,23 +170,25 @@ class PCSRX(LiteXModule):
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first_preamble_byte = Signal()
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self.comb += self.rx_data.eq(Mux(first_preamble_byte, 0x55, self.decoder.d))
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# Timer for SGMII data rates.
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timer = Signal(max=1000)
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timer_en = Signal()
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# SGMII Timer.
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# ------------
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timer = Signal(max=100)
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timer_enable = Signal()
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timer_done = Signal()
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self.comb += timer_done.eq(timer == 0)
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self.sync += [
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If(~timer_en | (timer == 0),
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timer.eq(timer - 1),
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If(~timer_enable | timer_done,
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Case(self.sgmii_speed, {
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0b00: timer.eq(99),
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0b01: timer.eq( 9),
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0b10: timer.eq( 0),
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SGMII_10MBPS_SPEED : timer.eq(99),
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SGMII_100MBPS_SPEED : timer.eq( 9),
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SGMII_1000MBPS_SPEED : timer.eq( 0),
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})
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).Elif(timer_en,
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timer.eq(timer - 1)
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)
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]
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# Speed adaptation
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self.comb += self.sample_en.eq(self.rx_en & (timer == 0))
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self.comb += self.sample_en.eq(self.rx_en & timer_done)
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self.fsm = fsm = FSM()
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fsm.act("START",
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@ -204,7 +198,7 @@ class PCSRX(LiteXModule):
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),
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If(self.decoder.d == K(27, 7),
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self.rx_en.eq(1),
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timer_en.eq(1),
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timer_enable.eq(1),
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first_preamble_byte.eq(1),
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NextState("DATA")
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)
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@ -228,7 +222,7 @@ class PCSRX(LiteXModule):
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If(self.decoder.k,
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If(self.decoder.d == K(27, 7),
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self.rx_en.eq(1),
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timer_en.eq(1),
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timer_enable.eq(1),
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first_preamble_byte.eq(1),
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NextState("DATA")
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).Else(
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@ -250,7 +244,7 @@ class PCSRX(LiteXModule):
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NextState("START")
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).Else(
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self.rx_en.eq(1),
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timer_en.eq(1)
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timer_enable.eq(1)
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)
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)
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@ -305,11 +299,7 @@ class PCS(LiteXModule):
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# # #
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# Endpoint interface.
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self.comb += [
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self.tx.tx_valid.eq(self.sink.valid),
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self.sink.ready.eq(self.tx.tx_ready),
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self.tx.tx_data.eq(self.sink.data),
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]
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self.comb += self.sink.connect(self.tx.sink, omit={"last_be", "error"})
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rx_en_d = Signal()
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self.sync.eth_rx += [
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