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Merge pull request #127 from rowanG077/master 

Add core CDC depth and buffered parameters.
This commit is contained in:
enjoy-digital 2023-07-03 18:57:24 +02:00 committed by GitHub
parent 6bdc13bb07 815c742c74
commit 322d8625b5
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 85 additions and 21 deletions
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21
liteeth/core/__init__.py
View File

@ -2,6 +2,7 @@
# This file is part of LiteEth.
#
# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2023 LumiGuide Fietsdetectie B.V. <goemansrowan@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
from liteeth.common import *
@ -17,7 +18,11 @@ class LiteEthIPCore(Module, AutoCSR):
def __init__(self, phy, mac_address, ip_address, clk_freq, dw=8,
with_icmp = True,
with_ip_broadcast = True,
with_sys_datapath = False):
with_sys_datapath = False,
tx_cdc_depth = 32,
tx_cdc_buffered = False,
rx_cdc_depth = 32,
rx_cdc_buffered = False):
# Parameters.
# -----------
ip_address = convert_ip(ip_address)
@ -30,6 +35,10 @@ class LiteEthIPCore(Module, AutoCSR):
interface = "crossbar",
with_preamble_crc = True,
with_sys_datapath = with_sys_datapath,
tx_cdc_depth = tx_cdc_depth,
tx_cdc_buffered = tx_cdc_buffered,
rx_cdc_depth = rx_cdc_depth,
rx_cdc_buffered = rx_cdc_buffered
)
# ARP.
@ -67,7 +76,11 @@ class LiteEthUDPIPCore(LiteEthIPCore):
def __init__(self, phy, mac_address, ip_address, clk_freq, dw=8,
with_icmp = True,
with_ip_broadcast = True,
with_sys_datapath = False):
with_sys_datapath = False,
tx_cdc_depth = 32,
tx_cdc_buffered = False,
rx_cdc_depth = 32,
rx_cdc_buffered = False):
# Parameters.
# -----------
ip_address = convert_ip(ip_address)
@ -83,6 +96,10 @@ class LiteEthUDPIPCore(LiteEthIPCore):
dw = dw,
with_ip_broadcast = with_ip_broadcast,
with_sys_datapath = with_sys_datapath,
tx_cdc_depth = tx_cdc_depth,
tx_cdc_buffered = tx_cdc_buffered,
rx_cdc_depth = rx_cdc_depth,
rx_cdc_buffered = rx_cdc_buffered
)
# UDP.
# ----

39
liteeth/gen.py
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@ -7,6 +7,7 @@
# Copyright (c) 2020 Xiretza <xiretza@xiretza.xyz>
# Copyright (c) 2020 Stefan Schrijvers <ximin@ximinity.net>
# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
# Copyright (c) 2023 LumiGuide Fietsdetectie B.V. <goemansrowan@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
"""
@ -281,9 +282,13 @@ class PHYCore(SoCMini):
class MACCore(PHYCore):
def __init__(self, platform, core_config):
# Parameters -------------------------------------------------------------------------------
nrxslots = core_config.get("nrxslots", 2)
ntxslots = core_config.get("ntxslots", 2)
bus_standard = core_config["core"]
nrxslots = core_config.get("nrxslots", 2)
ntxslots = core_config.get("ntxslots", 2)
bus_standard = core_config["core"]
tx_cdc_depth = core_config.get("tx_cdc_depth", 32)
tx_cdc_buffered = core_config.get("tx_cdc_buffered", False)
rx_cdc_depth = core_config.get("rx_cdc_depth", 32)
rx_cdc_buffered = core_config.get("rx_cdc_buffered", False)
assert bus_standard in ["wishbone", "axi-lite"]
# PHY --------------------------------------------------------------------------------------
@ -291,13 +296,18 @@ class MACCore(PHYCore):
# MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = ethmac = LiteEthMAC(
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = core_config["endianness"],
nrxslots = nrxslots,
ntxslots = ntxslots,
full_memory_we = core_config.get("full_memory_we", False))
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = core_config["endianness"],
nrxslots = nrxslots,
ntxslots = ntxslots,
full_memory_we = core_config.get("full_memory_we", False),
tx_cdc_depth = tx_cdc_depth
tx_cdc_buffered = tx_cdc_buffered
rx_cdc_depth = rx_cdc_depth
rx_cdc_buffered = rx_cdc_buffered
)
if bus_standard == "wishbone":
# Wishbone Interface -----------------------------------------------------------------------
@ -328,6 +338,10 @@ class UDPCore(PHYCore):
from liteeth.frontend.stream import LiteEthUDPStreamer
# Config -----------------------------------------------------------------------------------
tx_cdc_depth = core_config.get("tx_cdc_depth", 32)
tx_cdc_buffered = core_config.get("tx_cdc_buffered", False)
rx_cdc_depth = core_config.get("rx_cdc_depth", 32)
rx_cdc_buffered = core_config.get("rx_cdc_buffered", False)
# MAC Address.
mac_address = core_config.get("mac_address", None)
@ -355,6 +369,11 @@ class UDPCore(PHYCore):
clk_freq = core_config["clk_freq"],
dw = data_width,
with_sys_datapath = (data_width == 32),
tx_cdc_depth = tx_cdc_depth
tx_cdc_buffered = tx_cdc_buffered
rx_cdc_depth = rx_cdc_depth
rx_cdc_buffered = rx_cdc_buffered
)
# DHCP -------------------------------------------------------------------------------------

13
liteeth/mac/__init__.py
View File

@ -2,6 +2,7 @@
# This file is part of LiteEth.
#
# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2023 LumiGuide Fietsdetectie B.V. <goemansrowan@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
from liteeth.common import *
@ -21,7 +22,11 @@ class LiteEthMAC(Module, AutoCSR):
hw_mac = None,
timestamp = None,
full_memory_we = False,
with_sys_datapath = False):
with_sys_datapath = False,
tx_cdc_depth = 32,
tx_cdc_buffered = False,
rx_cdc_depth = 32,
rx_cdc_buffered = False):
assert dw%8 == 0
assert interface in ["crossbar", "wishbone", "hybrid"]
@ -31,7 +36,11 @@ class LiteEthMAC(Module, AutoCSR):
phy = phy,
dw = dw,
with_sys_datapath = with_sys_datapath,
with_preamble_crc = with_preamble_crc
with_preamble_crc = with_preamble_crc,
tx_cdc_depth = tx_cdc_depth,
tx_cdc_buffered = tx_cdc_buffered,
rx_cdc_depth = rx_cdc_depth,
rx_cdc_buffered = rx_cdc_buffered
)
self.csrs = []
if interface == "crossbar":

16
liteeth/mac/core.py
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@ -5,6 +5,7 @@
# Copyright (c) 2015-2017 Sebastien Bourdeauducq <sb@m-labs.hk>
# Copyright (c) 2021 David Sawatzke <d-git@sawatzke.dev>
# Copyright (c) 2017-2018 whitequark <whitequark@whitequark.org>
# Copyright (c) 2023 LumiGuide Fietsdetectie B.V. <goemansrowan@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
from liteeth.common import *
@ -21,7 +22,12 @@ class LiteEthMACCore(Module, AutoCSR):
def __init__(self, phy, dw,
with_sys_datapath = False,
with_preamble_crc = True,
with_padding = True):
with_padding = True,
tx_cdc_depth = 32,
tx_cdc_buffered = False,
rx_cdc_depth = 32,
rx_cdc_buffered = False,
):
# Endpoints.
self.sink = stream.Endpoint(eth_phy_description(dw))
@ -57,7 +63,9 @@ class LiteEthMACCore(Module, AutoCSR):
tx_cdc = stream.ClockDomainCrossing(eth_phy_description(core_dw),
cd_from = "sys",
cd_to = "eth_tx",
depth = 32)
depth = tx_cdc_depth,
buffered = tx_cdc_buffered
)
self.submodules += tx_cdc
self.pipeline.append(tx_cdc)
@ -186,7 +194,9 @@ class LiteEthMACCore(Module, AutoCSR):
rx_cdc = stream.ClockDomainCrossing(eth_phy_description(core_dw),
cd_from = "eth_rx",
cd_to = "sys",
depth = 32)
depth = rx_cdc_depth,
buffered = rx_cdc_buffered
)
self.submodules += rx_cdc
self.pipeline.append(rx_cdc)

17
liteeth/phy/ecp5rgmii.py
View File

@ -148,7 +148,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
# LiteEth PHY RGMII CRG ----------------------------------------------------------------------------
class LiteEthPHYRGMIICRG(LiteXModule):
def __init__(self, clock_pads, pads, with_hw_init_reset, tx_delay=2e-9):
def __init__(self, clock_pads, pads, with_hw_init_reset, tx_delay=2e-9, with_phy_tx_clock = None):
self._reset = CSRStorage()
# # #
@ -159,7 +159,14 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# TX Clock
self.cd_eth_tx = ClockDomain()
self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
if isinstance(with_phy_tx_clock, Signal):
phy_tx_clock = with_phy_tx_clock
else:
phy_tx_clock = self.cd_eth_rx.clk
self.comb += self.cd_eth_tx.clk.eq(phy_tx_clock)
tx_delay_taps = int(tx_delay/25e-12) # 25ps per tap
assert tx_delay_taps < 128
@ -201,8 +208,10 @@ class LiteEthPHYRGMII(LiteXModule):
def __init__(self, clock_pads, pads, with_hw_init_reset=True,
tx_delay = 2e-9,
rx_delay = 2e-9,
with_inband_status = True):
self.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
with_inband_status = True,
with_phy_tx_clock = None
):
self.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay, with_phy_tx_clock)
self.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay, with_inband_status))
self.sink, self.source = self.tx.sink, self.rx.source