diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py
index e284811..6ea7d6e 100644
--- a/liteeth/core/arp.py
+++ b/liteeth/core/arp.py
@@ -44,10 +44,8 @@ class LiteEthARPTX(Module):
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
-            sink.ready.eq(1),
             NextValue(counter, 0),
             If(sink.valid,
-                sink.ready.eq(0),
                 NextState("SEND")
             )
         )