From 355ac6ca5d453a97fae5d8478114a29eed07b6cd Mon Sep 17 00:00:00 2001
From: Matt Johnston <matt@codeconstruct.com.au>
Date: Tue, 6 Sep 2022 10:52:39 +0800
Subject: [PATCH] liteeth/gen: Use hw_init_reset for rgmii

This re-enables hw_init_reset that was disabled in
ea24ff6 ("liteeth_gen:  improve readability and add clk_freq checks.")

A chip reset is necessary using the Microchip KSZ9031RNX
PHY on an antmicro-artix-dc-scm board (possibly depending on startup
power timing)
---
 liteeth/gen.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/liteeth/gen.py b/liteeth/gen.py
index 8428599..e6f7946 100755
--- a/liteeth/gen.py
+++ b/liteeth/gen.py
@@ -204,7 +204,7 @@ class PHYCore(SoCMini):
                 pads               = platform.request("rgmii_eth"),
                 tx_delay           = core_config.get("phy_tx_delay", 2e-9),
                 rx_delay           = core_config.get("phy_rx_delay", 2e-9),
-                with_hw_init_reset = False) # FIXME: required since sys_clk = eth_rx_clk.
+            )
         else:
             raise ValueError("Unsupported PHY")
         self.submodules.ethphy = ethphy