From 36399d65da5d57fb0e0ad4de98d6a4881c53e5b1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 10 Feb 2016 10:28:41 +0100 Subject: [PATCH] example_designs/targets/core: add possibility to build udp cores (with hw udp/ip stack) --- example_designs/targets/core.py | 130 ++++++++++++++++++++++++++------ 1 file changed, 108 insertions(+), 22 deletions(-) diff --git a/example_designs/targets/core.py b/example_designs/targets/core.py index 80203ec..1edfa23 100644 --- a/example_designs/targets/core.py +++ b/example_designs/targets/core.py @@ -11,30 +11,20 @@ from litex.soc.interconnect import wishbone from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * +from liteeth.common import * + from liteeth.phy.mii import LiteEthPHYMII from liteeth.phy.rmii import LiteEthPHYRMII from liteeth.phy.gmii import LiteEthPHYGMII from liteeth.phy.s7rgmii import LiteEthPHYRGMII + from liteeth.core.mac import LiteEthMAC +from liteeth.core import LiteEthUDPIPCore _io = [ ("sys_clock", 0, Pins(1)), ("sys_reset", 1, Pins(1)), - ("wishbone", 0, - Subsignal("adr", Pins(30)), - Subsignal("dat_r", Pins(32)), - Subsignal("dat_w", Pins(32)), - Subsignal("sel", Pins(4)), - Subsignal("cyc", Pins(1)), - Subsignal("stb", Pins(1)), - Subsignal("ack", Pins(1)), - Subsignal("we", Pins(1)), - Subsignal("cti", Pins(3)), - Subsignal("bte", Pins(2)), - Subsignal("err", Pins(1)) - ), - # MII PHY Pads ("mii_eth_clocks", 0, Subsignal("tx", Pins(1)), @@ -103,6 +93,52 @@ _io = [ Subsignal("tx_ctl", Pins(1)), Subsignal("tx_data", Pins(4)) ), + + # Wishbone + ("wishbone", 0, + Subsignal("adr", Pins(30)), + Subsignal("dat_r", Pins(32)), + Subsignal("dat_w", Pins(32)), + Subsignal("sel", Pins(4)), + Subsignal("cyc", Pins(1)), + Subsignal("stb", Pins(1)), + Subsignal("ack", Pins(1)), + Subsignal("we", Pins(1)), + Subsignal("cti", Pins(3)), + Subsignal("bte", Pins(2)), + Subsignal("err", Pins(1)) + ), + + # UDP + ("udp_sink", 0, + Subsignal("stb", Pins(1)), + Subsignal("sop", Pins(1)), + Subsignal("eop", Pins(1)), + Subsignal("ack", Pins(1)), + # param + Subsignal("src_port", Pins(16)), + Subsignal("dst_port", Pins(16)), + Subsignal("ip_address", Pins(32)), + Subsignal("length", Pins(16)), + # payload + Subsignal("data", Pins(32)), + Subsignal("error", Pins(4)) + ), + + ("udp_source", 0, + Subsignal("stb", Pins(1)), + Subsignal("sop", Pins(1)), + Subsignal("eop", Pins(1)), + Subsignal("ack", Pins(1)), + # param + Subsignal("src_port", Pins(16)), + Subsignal("dst_port", Pins(16)), + Subsignal("ip_address", Pins(32)), + Subsignal("length", Pins(16)), + # payload + Subsignal("data", Pins(32)), + Subsignal("error", Pins(4)) + ), ] class CorePlatform(XilinxPlatform): @@ -135,7 +171,7 @@ class Core(SoCCore): } mem_map.update(SoCCore.mem_map) - def __init__(self, phy, clk_freq=100*1000000): + def __init__(self, phy, core, clk_freq, mac_address, ip_address, udp_port): platform = CorePlatform() SoCCore.__init__(self, platform, clk_freq=clk_freq, @@ -163,23 +199,73 @@ class Core(SoCCore): else: ValueError("Unsupported " + phy + " PHY"); - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + # core + if core == "mac": + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") + self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) - # wishbone - self.add_cpu_or_bridge(WishboneBridge(platform.request("wishbone"))) - self.add_wb_master(self.cpu_or_bridge.wishbone) + self.add_cpu_or_bridge(WishboneBridge(platform.request("wishbone"))) + self.add_wb_master(self.cpu_or_bridge.wishbone) + + elif core == "udp": + self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), clk_freq) + udp_port = self.core.udp.crossbar.get_port(udp_port, 8) + # XXX avoid manual connect + udp_sink = platform.request("udp_sink") + self.comb += [ + # control + udp_port.sink.stb.eq(udp_sink.stb), + udp_port.sink.sop.eq(udp_sink.sop), + udp_port.sink.eop.eq(udp_sink.eop), + udp_sink.ack.eq(udp_port.sink.ack), + # param + udp_port.sink.src_port.eq(udp_sink.src_port), + udp_port.sink.dst_port.eq(udp_sink.dst_port), + udp_port.sink.ip_address.eq(udp_sink.ip_address), + udp_port.sink.length.eq(udp_sink.length), + + # payload + udp_port.sink.data.eq(udp_sink.data), + udp_port.sink.error.eq(udp_sink.error) + ] + udp_source = platform.request("udp_source") + self.comb += [ + # control + udp_source.stb.eq(udp_port.source.stb), + udp_source.sop.eq(udp_port.source.sop), + udp_source.eop.eq(udp_port.source.eop), + udp_port.source.ack.eq(udp_source.ack), + + # param + udp_source.src_port.eq(udp_port.source.src_port), + udp_source.dst_port.eq(udp_port.source.dst_port), + udp_source.ip_address.eq(udp_port.source.ip_address), + udp_source.length.eq(udp_port.source.length), + + # payload + udp_source.data.eq(udp_port.source.data), + udp_source.error.eq(udp_port.source.error) + ] def main(): parser = argparse.ArgumentParser(description="LiteEth core builder") builder_args(parser) soc_core_args(parser) parser.add_argument("--phy", default="MII", help="Ethernet PHY(MII/RMII/GMII/RMGII)") + parser.add_argument("--core", default="wishbone", help="Ethernet Core(wishbone/udp)") + parser.add_argument("--mac_address", default=0x10e2d5000000, help="MAC address") + parser.add_argument("--ip_address", default="192.168.0.42", help="IP address") args = parser.parse_args() - soc = Core(phy=args.phy, **soc_core_argdict(args)) + soc = Core(phy=args.phy, + core=args.core, + clk_freq=100*1000, + mac_address=args.mac_address, + ip_address=args.ip_address, + udp_port=6000, + **soc_core_argdict(args)) builder = Builder(soc, output_dir="liteeth", compile_gateware=False, csr_csv="liteeth/csr.csv") builder.build(build_name="liteeth")