From 3696ef82bb9bc9cbd53b7536c3065697806626e8 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 26 Sep 2024 11:03:12 +0200 Subject: [PATCH] phy/trionrgmii,titaniumrgmii: replaces str by ClockSignal for ClkInput and PLL --- liteeth/phy/titaniumrgmii.py | 4 ++-- liteeth/phy/trionrgmii.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/liteeth/phy/titaniumrgmii.py b/liteeth/phy/titaniumrgmii.py index ed87648..c05f3d0 100644 --- a/liteeth/phy/titaniumrgmii.py +++ b/liteeth/phy/titaniumrgmii.py @@ -131,7 +131,7 @@ class LiteEthPHYRGMIICRG(LiteXModule): # ------- self.specials += ClkInput( i = clock_pads.rx, - o = f"auto_eth{n}_rx_clk_in", # FIXME: Use Clk Signal. + o = self.cd_eth_rx.clk, ) # TX Clk. @@ -144,7 +144,7 @@ class LiteEthPHYRGMIICRG(LiteXModule): # TX PLL. # ------- self.pll = pll = TITANIUMPLL(platform) - pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput + pll.register_clkin(self.cd_eth_rx.clk, freq=125e6) pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False) pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False) pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=90) diff --git a/liteeth/phy/trionrgmii.py b/liteeth/phy/trionrgmii.py index 3ccc7c5..4812747 100644 --- a/liteeth/phy/trionrgmii.py +++ b/liteeth/phy/trionrgmii.py @@ -131,7 +131,7 @@ class LiteEthPHYRGMIICRG(LiteXModule): # ------- self.specials += ClkInput( i = clock_pads.rx, - o = f"auto_eth{n}_rx_clk_in", # FIXME: Use Clk Signal. + o = self.cd_eth_rx.clk, ) # TX Clk. @@ -144,7 +144,7 @@ class LiteEthPHYRGMIICRG(LiteXModule): # TX PLL. # ------- self.pll = pll = TRIONPLL(platform) - pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput + pll.register_clkin(self.cd_eth_rx.clk, freq=125e6) pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False, is_feedback=True) pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False) pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=45)